Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

power measurement hardware for multiple subsystems, measurement need only be
implemented on a single system during the design stage. The model is created based on
measurement from a small number of systems which allows power measurement
hardware to be eliminated from the final product.
While the trickle-down approach simplifies power modeling of complete systems it
requires a modest knowledge of subsystem level interaction. The effectiveness of the
model at capturing system-level power is determined by the selection of comprehensive
performance events. Some events such as top-level cache or memory accesses are
intuitive. A miss in the first level cache will necessarily generate traffic in higher level
caches and or the memory subsystem. Other events such as those found in I/O devices
are not as obvious. Consider the system diagram in Figure 5.1.
This represents the quad-socket server for which the trickle-down modeling approach is
applied. The arrows flowing outward from the processor represent events that originate
in the processor and trickle-down to other subsystems (L3 Miss, TLB Miss, MemBus
Access and Uncacheable Access). Arrows flowing inward such as DMA (Direct
Memory Access) or bus master access and I/O interrupts may not be directly generated
by the processor, but are nevertheless visible. Since DMA access is typically performed
to addresses marked as cacheable by the processor, they can be observed in the standard
cache access metrics. To distinguish DMA accesses by a particular device, events should
be qualified by address range. Each device typically uses a private range of addresses in
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