Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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I/O device. The transfer size, source and destination are specified through the memory mapped I/O space. The disk controller performs the transfer without further intervention from the microprocessor. Upon completion or incremental completion (buffer full/empty) the I/O device interrupts the microprocessor. The microprocessor is then able to use the requested data or discard local copies of data that was sent. This study uses the number of interrupts originating from the disk controller. This approach has the advantage over the other metrics in that the events are specific to the subsystem of interest. This approach is able to represent fine-grain variation with low error. In the case of the synthetic disk workload, by using the number of disk interrupts/cycle an average error rate of 1.75% is achieved. The model is provided in Equation 5.4. An application of the model to the memory-intensive mcf is shown in Figure 5.6. Note that this error rate accounts for the large DC offset within the disk power consumption. This error is calculated by first subtracting the 21.6W of idle (DC) disk power consumption. The remaining quantity is used for the error calculation. NumCPUs + ∑ i = 1 21. 6 + DMAAccess Cycle Interrupts i Cycle × 9. 18 − i × 10. 6 ⋅10 Cycle 78 7 DMAAccess − 2 i Interrupt × Cycle 45. 4 2 i × 11. 1 ⋅10 15 (5.4)
Watts Figure 5.6 Disk Power Model (DMA+Interrupt) – Synthetic Disk Workload 5.2.4 I/O Since the majority of I/O transactions are DMA transactions from the various I/O controllers, an I/O power model must be sensitive to these events. Three events are considered to observe DMA traffic: DMA accesses on memory bus, uncacheable accesses and interrupts. Of the three, interrupts/cycle is the most representative. DMA accesses to main memory seemed to be the logical best choice since there is such a close relation to the number of DMA accesses and the switching factor in the I/O chips. For example, a transfer of cache line aligned 16 dwords (4 bytes/dword), maps to a single cache line transfer on the processor memory bus. However, in the case of smaller, non- aligned transfers the linear relationship does not hold. A cache line access measured as a single DMA event from the microprocessor perspective may contain only a single byte. This would grossly overestimate the power being consumed in the I/O subsystem. Further complicating the situation is the presence of performance enhancements in the I/O chips. 22.4 22.2 22 21.8 79 100% 50% 21.6 21.4 Measured Modeled Error -50% 21.2 -100% 0 100 200 Seconds 300 400 0% Error (%)
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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Page 45 and 46: Table 3.4 Instruction Linear Regres
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Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
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Page 59 and 60: 3.6 Summary This section describes
Page 61 and 62: Power (Watts) 30 25 20 15 10 5 0 Co
Page 63 and 64: workloads become more memory-bound,
Page 65 and 66: At the other extreme, the productiv
Page 67 and 68: processor. In both platforms the to
Page 69 and 70: Table 4.1 Subsystem Power Standard
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Page 75 and 76: Table 4.4 Workload Phase Classifica
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Page 81 and 82: power measurement hardware for mult
Page 83 and 84: memory. Since the number of main me
Page 85 and 86: TLB Misses - Loads/stores that miss
Page 87 and 88: The form of the subsystem power mod
Page 89 and 90: 5.2.2 Memory This section considers
Page 91 and 92: prefetch traffic does increase afte
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Page 97 and 98: exhibits little variation in power
Page 99 and 100: The memory model averaged about 9%
Page 101 and 102: efficiency rather than performance.
Page 103 and 104: through the application GUI. The nu
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Page 107 and 108: periods of disconnect, cache snoop
Page 109 and 110: 5.3.4 CPU To test the extensibility
Page 111 and 112: Despite this, high accuracy of less
Page 113 and 114: Light activity yields higher precha
Page 115 and 116: 5.3.8 Chipset The Chipset power mod
Page 117 and 118: applied to the GPU core logic, larg
Page 119 and 120: Chapter 6 Performance Effects of Dy
Page 121 and 122: can be considered as predictors whi
Page 123 and 124: improvement for low idle core frequ
Page 125 and 126: 6.1.5 Direct Performance Effects Si
Page 127 and 128: of SPEC CPU2000 workloads, almost n
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Page 133 and 134: In order to reduce p-state performa
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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