Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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[RaLe06] P. Ranganathan, P. Leech, D. Irwin, and J. Chase. Ensemble-Level Power Management for Dense Blade Servers. In Proceedings of the 33 rd International Symposium on Computer Architecture (Boston, Massachusetts, June 2006), 66-77. [SiPa07] S. Siddah, V. Pallipadi, and A. Van de Ven. Getting Maximum Mileage Out of Tickless. In Proceedings of the 9 th Linux Symposium (Ottawa, Canada, June 2007), 201-207. [Sp00] SPEC CPU 2000 Version 1.3, www.spec.org/cpu2000, October 2006. [Sp06] SPEC CPU 2006 Version 1.1, www.spec.org/cpu2006, October 2006. [Sj06] SPECjbb 2005 Version 1.07, www.spec.org/jbb2005, October 2006. [Sp02] B. Sprunt. Pentium 4 Performance Monitoring Features, Micro, July- August, pp 72-82, 2002. [Se06] Texas Instruments. INA168 High-Side Measurement Current Shunt Monitor. ti.com, May 2006. [Sm07] Business Applications Performance Corporation. SYSmark 2007 an Overview of SYSmark 2007 Preview, May 2008. [3d06] Futuremark. 3DMark06 Whitepaper v1.02, January 2006. 170
[WaCh08] X. Wang and M. Chen. Cluster Level Feedback Power Control for Performance Optimization. In Proceedings of the 14 th International Symposium on High- Performance Computer Architecture (Salt Lake City, Utah, February 2008), 101-110. [Mm05] Windows Multimedia: timeEndPeriod(). http://msdn.microsoft.com/en- us/library/ms713415(VS.85).aspx (November 2008). [WuJu05] Q. Wu, P. Juang, M. Martonosi, L. Peh, and D. Clark. Formal control techniques for power-performance management. IEEE Micro, 25, 5 (September/October 2005). [ZeSo03] J. Zedlewski, S. Sobti, N. Garg, F. Zheng, A. Krishnamurthyy, and R. Wang. Modeling Hard-Disk Power Consumption. File and Storage Technologies 2003. [ShSc08] A. Shye, Y. Pan, B. Scholbrock, J.S. Miller, G. Memik, P.A. Dinda and R.P. Dick. Power to the People: Leveraging Human Physiological Traits to Control Microprocessor Frequency Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction. In Proceedings of 41st IEEE/ACM International Symposium on Microarchitecture, (Lake Como, Italy, November 2008), 188-199. [ShOz08] A. Shye, B. Ozisikyilmaz, A. Mallik, G. Memik , P.A. Dinda , R.P. Dick and A.N. Choudhary. Learning and Leveraging the Relationship between Architecture- Level Measurements and Individual User Satisfaction. In Proceedings of the 35th 171
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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Page 169 and 170: Chapter 9 Conclusions and Future Wo
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Page 175 and 176: [BiJo06-1] W. L. Bircher and L. Joh
Page 177 and 178: the 2005 ACM SIGMETRICS Internation
Page 179 and 180: [HaKe07] H. Hanson, S.W. Keckler, K
Page 181 and 182: [JoMa01] R. Joseph and M. Martonosi
Page 183 and 184: [LiBr05] Y. Li, D. Brooks, Z. Hu, a
Page 185: [Os06] Open Source Development Lab,
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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