Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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activity levels to 30%. Since processors have a finite number of architected DVFS states, the algorithm selects the nearest frequency which meets the target activity level. Core Activity Level 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% = Increase Frequency Increase Threshold = 50% No Change Decrease Threshold = 30% Decrease Frequency 126 + Figure 7.2: Windows Vista Reactive P-State Selection Algorithm 7.3 Workload Characterization High Performance Demand Region Hysteresis Region Low Performance Demand Region To analyze the power/performance impact of the predictive power management scheme on real-world workloads, a system running the desktop/client SYSmark 2007 benchmark is characterized. This benchmark represents a wide range of desktop computing applications. The benchmark components are E-Learning, Video Creation, Productivity, and 3D. The individual subtests are listed in Table 7.1. This benchmark is particularly important to the study of dynamic power adaptations since it provides realistic user scenarios that include user interface and I/O delays. These delays cause a large amount
of idle-active transitions in the cores. Since current OSs determine dynamic adaption levels using core activity level, the replication of these user interactions in the benchmark is critical. For comparison, Figure 7.3 shows average active core residencies of a six- core AMD Phenom 2 processor across a wide range of desktop workloads. The left-hand side of the figure illustrates the problem with many popular benchmark applications. The benchmarks spend nearly 100% of the time with all cores active. From an idle power management perspective little can be done to improve performance and power efficiency. The center and right-hand side workloads are more challenging for idle power management due to the frequent occurrence of idle phases. The SYSmark subtests are the most challenging due to their large composition of interspersed idle and active phases. Table 7.1: SYSmark 2007 Components E-Learning Video Creation Productivity 3D Adobe - Illustrator - Photoshop -Flash Microsoft - PowerPoint Adobe - After Effects - Illustrator - Photoshop Microsoft - Media Encoder Sony - Vegas Microsoft - Excel - Outlook - Word - PowerPoint - Project Corel - WinZip 127 Autodesk - 3Ds Max Google - SketchUp Performance Loss for Vista Reactive Power Management [4] 8.8% 6.2% 9.5% 5.9%
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Copyright by William Lloyd Bircher
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Predictive Power Management for Mul
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Acknowledgements I would like to th
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Predictive Power Management for Mul
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Table of Contents Chapter 1 Introdu
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5.3.6 Memory ......................
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List of Tables Table 1.1 Windows Vi
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List of Figures Figure 1.1 CPU Core
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Chapter 1 Introduction Computing sy
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increases the overhead of adaptatio
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suboptimal from a power and perform
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Active Core Activity Idle except fo
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4. Design a predictive power manage
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1.7 Organization This dissertation
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Chapter 2 Methodology The developme
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2.1.2 Subsystem-Level Power in a Se
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The main components are subsystem p
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Table 2.4 Laptop System Description
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2.3 Performance Counter Sampling To
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instruction streams that exercise a
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the power trace to the PMC trace co
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The first bar in Figure 3.1 “Fetc
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Table 3.4 Instruction Linear Regres
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long time to complete, more aggress
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power adaptations as c-states. Thes
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Core Power (Watts) 60 50 40 30 20 1
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The difference between C0-Idle and
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case error is 3.3%. Alternatively s
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3. Based on basic domain knowledge,
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3.6 Summary This section describes
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Power (Watts) 30 25 20 15 10 5 0 Co
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workloads become more memory-bound,
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At the other extreme, the productiv
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processor. In both platforms the to
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Table 4.1 Subsystem Power Standard
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the case of I/O, the observed workl
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average distribution. The apparent
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Table 4.4 Workload Phase Classifica
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Frequency 1 10 100 1000 PhaseLength
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power management, it is shown that
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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Page 175 and 176: [BiJo06-1] W. L. Bircher and L. Joh
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Page 181 and 182: [JoMa01] R. Joseph and M. Martonosi
Page 183 and 184: [LiBr05] Y. Li, D. Brooks, Z. Hu, a
Page 185 and 186: [Os06] Open Source Development Lab,
Page 187 and 188: [WaCh08] X. Wang and M. Chen. Clust
Page 189 and 190: [PiSh01] P. Pillai and K. G. Shin.
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Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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