Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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2.1.1 Aggregate CPU Power Measurement CPU power consumption is measured using a clamp-on current probe. The probe, an Agilent 1146A [Ag08], reports current passing through its sensor by detecting the magnitude and polarity of the electromagnetic field produced by the sampled current. This type of measurement simplifies instrumentation since the observed conductors do not have to be cut to insert current sensing resistors. The drawback of this approach is that only wire-type conductors can be sampled. It is not possible to sample conductors embedded in the printed circuit board. For the target system this restricts power measurement to the input conductors of the processor voltage regulator module (VRM). As a result, a portion of the reported power consumption is actually attributed to the inefficiency of the VRM. These modules have an efficiency of 85%-90%. The reader should consider the 10%-15% loss when comparing results to manufacturer reported power consumption. The voltage provided by the current probe is sampled at 10 KHz by a National Instruments AT-MIO-16E-2 data acquisition card[Ni08]. The LabVIEW software tool [La10] can interpret the voltage trace or as in this case it is written to a binary file for offline processing. The details of the system are described below in Table 2.1. Table 2.1 Desktop System Description System Parameters Single Pentium 4 Xeon 2.0 GHz, 512KB L2 Cache, 2MB L3 Cache, 400 MHz FSB 4 GB PC133 SDRAM Main Memory Two 16GB Adaptec Ultra160 10K SCSI Disks Redhat Linux 14
2.1.2 Subsystem-Level Power in a Server System To study component-level server power, the aggregate CPU power measurement framework is used and extended to provide additional functionality required for subsystem-level study. The most significant difference between the studies of CPU level versus subsystem level is the requirement for simultaneously sampling multiple power domains. To meet this requirement the IBM x440 server is used which provides separate, measureable power rails for five major subsystems. It is described in Table 2.2. Table 2.2 Server System Description System Parameters Four Pentium 4 Xeon 2.0 GHz, 512KB L2 Cache, 2MB L3 Cache, 400 MHz FSB 32MB DDR L4 Cache 8 GB PC133 SDRAM Main Memory Two 32GB Adaptec Ultra160 10K SCSI Disks Fedora Core Linux, kernel 2.6.11 By choosing this server, instrumentation is greatly simplified due to the presence of current sensing resistors on the major subsystem power domains. Five power domains are considered: CPU, chipset, memory, I/O, and disk. The components of each subsystem are listed in Table 2.3. Table 2.3 Subsystem Components Subsystem Components CPU Four Pentium 4 Xeons Chipset Memory Controllers and Processor Interface Chips Memory System Memory and L4 Cache I/O I/O Bus Chips, SCSI, NIC Disk Two 10K rpm 32G Disks 15
Page 1 and 2: Copyright by William Lloyd Bircher
Page 3 and 4: Predictive Power Management for Mul
Page 5 and 6: Acknowledgements I would like to th
Page 7 and 8: Predictive Power Management for Mul
Page 9 and 10: Table of Contents Chapter 1 Introdu
Page 11 and 12: 5.3.6 Memory ......................
Page 13 and 14: List of Tables Table 1.1 Windows Vi
Page 15 and 16: List of Figures Figure 1.1 CPU Core
Page 17 and 18: Chapter 1 Introduction Computing sy
Page 19 and 20: increases the overhead of adaptatio
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Page 23 and 24: Active Core Activity Idle except fo
Page 25 and 26: 4. Design a predictive power manage
Page 27 and 28: 1.7 Organization This dissertation
Page 29: Chapter 2 Methodology The developme
Page 33 and 34: The main components are subsystem p
Page 35 and 36: Table 2.4 Laptop System Description
Page 37 and 38: 2.3 Performance Counter Sampling To
Page 39 and 40: instruction streams that exercise a
Page 41 and 42: the power trace to the PMC trace co
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Page 45 and 46: Table 3.4 Instruction Linear Regres
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Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
Page 53 and 54: The difference between C0-Idle and
Page 55 and 56: case error is 3.3%. Alternatively s
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Page 59 and 60: 3.6 Summary This section describes
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Page 69 and 70: Table 4.1 Subsystem Power Standard
Page 71 and 72: the case of I/O, the observed workl
Page 73 and 74: average distribution. The apparent
Page 75 and 76: Table 4.4 Workload Phase Classifica
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power measurement hardware for mult
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memory. Since the number of main me
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TLB Misses - Loads/stores that miss
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The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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performance loss and power consumpt
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eactive scheme used in Windows Vist
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Watts Watts Watts Watts Watts 150 1
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7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
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[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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