Copyright by William Lloyd Bircher 2010 - The Laboratory for ...

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instruction stream lasting only a few microseconds, dynamic power management must also consider long duration phases ranging from hundreds to millions of microseconds. These phases, caused by events such as thread migrations, context switches or device interrupts provide greater opportunity (and challenge) for power management due to the longer time for amortizing adaptation costs. To this end, this dissertation analyzes power consumption, modeling and prediction across over sixty distinct subtests. The workloads and their characteristics are listed in Table 2.5. Name [Subtest Count] SPEC CPU 2000 [26] SPEC CPU 2006 [29] SPECjbb 2005 [1] DBT-2 [1] SYSmark 2007 [4] 3DMark 2006 [6] Idle [1] Table 2.5 Workload Description Workload Subsystem Type Target Scientific CPU DRAM Scientific CPU DRAM Transaction Processing CPU DRAM Database I/O Disk Productivity CPU DRAM I/O Disk 3D Gaming Graphics CPU DRAM 22 Phase Behavior Systems Analyzed Instruction Server Desktop Laptop Instruction Server Desktop Laptop Instruction Server Instruction Active-Idle Power Management Instruction Active-Idle Threadedness Power Management Instruction Active-Idle Power Management Server Desktop Laptop Laptop Idle CPU Active-Idle Server, Desktop Laptop To develop power models for active execution (non-idle) the SPEC CPU 2000, 2006 and SPECjbb 2005 workloads are used [Sp00] [Sp06] [Sj06]. These workloads contain
instruction streams that exercise a wide range of intensities in the CPU and memory subsystems. They include integer and floating centric workloads. Within these two types the focus varies from workloads completely bound by CPU execution speed to those bound be memory access latency and throughput. These benchmarks provide sufficient information to develop active power models for CPU and memory. The limitation is that they operate in an unrealistic fully-active mode utilization only the CPU and memory subsystems. Unlike real usage scenarios, these workloads do not frequently transition between the active and idle states or exercise disk, graphics or I/O subsystems. To address this limitation the DBT-2, SYSmark 2007 and 3DMark 2006 benchmarks are included. These workloads emulate real usage scenarios by including user-input and system interactions. DBT-2 [Os06] is intended to approximate the TPC-C transaction processing benchmark. This workload does not require network clients, but does use actual hard disk access through the PostgreSQL [PS06] database. SYSmark 2007 [Sm07] is implemented using simulated user input through the application GUI (graphical user interface). The numerous delays required for GUI interaction causes many idle phases across the subsystems. This causes a large degree of active-idle and idle-active transitions, thread migrations and power management events. 3DMark06 [3d06] contains six subtests covering CPU and graphics-intensive workloads. Additionally, systems are characterized in the idle state. This sets a baseline for power consumption and represents common usage patterns. 23
Page 1 and 2: Copyright by William Lloyd Bircher
Page 3 and 4: Predictive Power Management for Mul
Page 5 and 6: Acknowledgements I would like to th
Page 7 and 8: Predictive Power Management for Mul
Page 9 and 10: Table of Contents Chapter 1 Introdu
Page 11 and 12: 5.3.6 Memory ......................
Page 13 and 14: List of Tables Table 1.1 Windows Vi
Page 15 and 16: List of Figures Figure 1.1 CPU Core
Page 17 and 18: Chapter 1 Introduction Computing sy
Page 19 and 20: increases the overhead of adaptatio
Page 21 and 22: suboptimal from a power and perform
Page 23 and 24: Active Core Activity Idle except fo
Page 25 and 26: 4. Design a predictive power manage
Page 27 and 28: 1.7 Organization This dissertation
Page 29 and 30: Chapter 2 Methodology The developme
Page 31 and 32: 2.1.2 Subsystem-Level Power in a Se
Page 33 and 34: The main components are subsystem p
Page 35 and 36: Table 2.4 Laptop System Description
Page 37: 2.3 Performance Counter Sampling To
Page 41 and 42: the power trace to the PMC trace co
Page 43 and 44: The first bar in Figure 3.1 “Fetc
Page 45 and 46: Table 3.4 Instruction Linear Regres
Page 47 and 48: long time to complete, more aggress
Page 49 and 50: power adaptations as c-states. Thes
Page 51 and 52: Core Power (Watts) 60 50 40 30 20 1
Page 53 and 54: The difference between C0-Idle and
Page 55 and 56: case error is 3.3%. Alternatively s
Page 57 and 58: 3. Based on basic domain knowledge,
Page 59 and 60: 3.6 Summary This section describes
Page 61 and 62: Power (Watts) 30 25 20 15 10 5 0 Co
Page 63 and 64: workloads become more memory-bound,
Page 65 and 66: At the other extreme, the productiv
Page 67 and 68: processor. In both platforms the to
Page 69 and 70: Table 4.1 Subsystem Power Standard
Page 71 and 72: the case of I/O, the observed workl
Page 73 and 74: average distribution. The apparent
Page 75 and 76: Table 4.4 Workload Phase Classifica
Page 77 and 78: Frequency 1 10 100 1000 PhaseLength
Page 79 and 80: power management, it is shown that
Page 81 and 82: power measurement hardware for mult
Page 83 and 84: memory. Since the number of main me
Page 85 and 86: TLB Misses - Loads/stores that miss
Page 87 and 88: The form of the subsystem power mod
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5.2.2 Memory This section considers
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prefetch traffic does increase afte
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average access time to the distant
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Watts Figure 5.6 Disk Power Model (
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exhibits little variation in power
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The memory model averaged about 9%
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efficiency rather than performance.
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through the application GUI. The nu
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1 data cache access rate dominates
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periods of disconnect, cache snoop
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5.3.4 CPU To test the extensibility
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Despite this, high accuracy of less
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Light activity yields higher precha
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5.3.8 Chipset The Chipset power mod
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applied to the GPU core logic, larg
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Chapter 6 Performance Effects of Dy
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can be considered as predictors whi
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improvement for low idle core frequ
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6.1.5 Direct Performance Effects Si
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of SPEC CPU2000 workloads, almost n
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adjusting a hysteresis timer. The t
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increase/decrease time. Since the i
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In order to reduce p-state performa
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performance loss and power consumpt
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eactive scheme used in Windows Vist
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Watts Watts Watts Watts Watts 150 1
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7.2 Commercial DVFS Algorithm Exist
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of idle-active transitions in the c
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workload/operating systems adds and
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instructions. In APCI[Ac07] termino
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confidence level will drop below a
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First, prediction accuracy is consi
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coverage of 43% and accuracy over 9
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which corresponds to the DVFS sched
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Table 7.6: SYSmark 2007 Power and P
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In this case the predictor achieves
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2007 power consumption contains man
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Chapter 8 Related Research This sec
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8.2 System-Level Power Characteriza
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prediction scheme in this dissertat
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Chapter 9 Conclusions and Future Wo
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the duration of power and performan
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execution, portions of pipelines or
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[BiJo06-1] W. L. Bircher and L. Joh
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the 2005 ACM SIGMETRICS Internation
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[HaKe07] H. Hanson, S.W. Keckler, K
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[JoMa01] R. Joseph and M. Martonosi
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[LiBr05] Y. Li, D. Brooks, Z. Hu, a
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[Os06] Open Source Development Lab,
Page 187 and 188:
[WaCh08] X. Wang and M. Chen. Clust
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[PiSh01] P. Pillai and K. G. Shin.
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