Quartus II Settings File Reference Manual - Altera

Chapter 4: Analysis & Synthesis Assignments 4–17
ALLOW_XOR_GATE_USAGE
ALLOW_XOR_GATE_USAGE
Type
Allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an
embedded cell within an Embedded System Block [ESB] that is set to use Product
Term mode). This option is ignored if you select LUT or ROM as the setting for the
Technology Mapper option.
This option is ignored if it is assigned to anything other than a design entity. The
Allow XOR Gate Usage option is also ignored if you select LUT or ROM as the setting
for the Technology Mapper option. This option can be set in the Assignment Editor
in the Assignments menu, the Analysis & Synthesis Settings page, or the Fitter
Settings page of the Settings dialog box in the Assignments menu. This option is
available for APEX 20K, APEX 20KC, APEX 20KE, APEX II, Excalibur, MAX 3000,
MAX 7000A, MAX 7000AE, MAX 7000B, and MAX 7000S devices.
This option is turned on by default.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ MAX3000A
■ MAX7000A
■ MAX7000AE
■ MAX7000B
■ MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ALLOW_XOR_GATE_USAGE
set_global_assignment -name ALLOW_XOR_GATE_USAGE -entity
set_instance_assignment -name ALLOW_XOR_GATE_USAGE -to -entity
Example
set_instance_assignment -name allow_xor_gate_usage off -to clock
Default Value
On
June 2012 Altera Corporation Quartus Settings File
Reference Manual