10.12.2012 Views

Quartus II Settings File Reference Manual - Altera

Quartus II Settings File Reference Manual - Altera

Quartus II Settings File Reference Manual - Altera

SHOW MORE
SHOW LESS

Create successful ePaper yourself

Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.

6–18 Chapter 6: Fitter Assignments<br />

AUTO_PACKED_REGISTERS_CYCLONE<br />

AUTO_PACKED_REGISTERS_CYCLONE<br />

Type<br />

Allows the Compiler to automatically implement a register and a combinational<br />

function in the same logic cell, or to implement registers using I/O cells or RAM<br />

blocks instead of logic cells. This option controls how aggressively the Fitter combines<br />

registers with other function blocks in order to reduce logic element count. If this<br />

option is set to Off, the Fitter does not attempt to place a pair of logic functions in a<br />

single logic cell; however, logic cells specified during synthesis to perform both a<br />

combinational and a sequential function are maintained. If this option is set to<br />

Normal, the Fitter places both a combinational and a sequential operation in a logic<br />

cell when it is expected that the placement does not affect design performance. When<br />

this option is set to Minimize Area, the Fitter aggressively combines unrelated<br />

sequential and combinational functions that are not part of an arithmetic or register<br />

cascade chain into a single logic cell in order to reduce the logic cell count, even at the<br />

expense of design performance. When this option is set to Minimize Area with<br />

Chains, the Fitter even more aggressively combines sequential and combinational<br />

functions that are part of arithmetic or register cascade chains or that can be converted<br />

to register cascade chains. When this setting is Auto, the fitter attempts to achieve the<br />

best performance while maintaining a fit for the design in the specified device. The<br />

fitter will combine all combinational and sequential functions that are deemed to<br />

benefit circuit speed. In addition, more aggressive combinations of unrelated<br />

combinational and sequential functions are performed to the extent required to<br />

reduce the area of the design in order to achieve a fit in the specified device. If this<br />

option is set to any value but Off, registers are merged with I/O cells to improve I/O<br />

timing, and with RAM blocks to reduce logic cell count or improve timing when<br />

possible.<br />

Enumeration<br />

■ Auto<br />

■ Minimize Area<br />

■ Minimize Area with Chains<br />

■ Normal<br />

■ Off<br />

Device Support<br />

This setting can be used in projects targeting the following device families:<br />

■ Cyclone<br />

Notes<br />

This assignment supports wildcards.<br />

This assignment is included in the Fitter report.<br />

Syntax<br />

set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE <br />

<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />

<strong>Reference</strong> <strong>Manual</strong>

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!