Quartus II Settings File Reference Manual - Altera

4–184 Chapter 4: Analysis & Synthesis Assignments
SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
Type
Specifies whether Analysis & Synthesis is allowed to use information about the device
and design resources to decide which logical RAMs, ROMs, and shift-registers to infer
from your HDL.
You can use this option when regular synthesis infers more RAMs, ROMs, and shiftregisters
to be implemented in block RAM than the device can fit. Resource-aware
inference tries to estimate the required number of RAM blocks and registers for your
design, and makes inference decisions based on the available device resources.
This option can only be used for Cyclone, Cyclone II, Cyclone III, Cyclone III LS,
Cyclone IV, Arria II GX, Stratix III, HardCopy III, Stratix IV and HardCopy IV
families. It is ignored for other families.
When you set this option to on, Altera recommends that you specify a device for the
design. If no device is specified, then the RAM, ROM, and shift-register inference is
not resource-aware.
This option can be used as a project-wide option only.
This option is turned on by default.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ Arria II GX
■ Arria II GZ
■ Arria V
■ Cyclone
■ Cyclone II
■ Cyclone III
■ Cyclone III LS
■ Cyclone IV E
■ Cyclone IV GX
■ Cyclone V
■ HardCopy II
■ HardCopy III
■ HardCopy IV
■ Stratix
■ Stratix II
■ Stratix III
Quartus Settings File June 2012 Altera Corporation
Reference Manual