Quartus II Settings File Reference Manual - Altera

6–254 Chapter 6: Fitter Assignments
PLL_AUTO_RESET
PLL_AUTO_RESET
Type
Causes the PLL to self-reset automatically on loss of lock. The lock time of a PLL is
defined as the amount of time required by the PLL to attain the target frequency and
phase relationship after device power-up, after a change in the PLL output frequency,
or after resetting the PLL.
A PLL might lose lock for a number of reasons, such as the following causes:
■ Excessive jitter on the reference clock. For PLL input jitter specification, refer to the
DC and Switching Characteristics chapter in the relevant device handbook.
■ Excessive switching noise on the clock inputs of the PLL.
■ Excessive noise from the power supply can cause high output jitter and possible
loss of lock.
■ A glitch or stopping of the input clock to the PLL.
■ Resetting the PLL by asserting the reset port of the PLL.
■ An attempt to reconfigure the PLL might cause the M counter, N counter, or phase
shift to change, which causes the PLL to lose lock. However, changes to the postscale
counters do not affect the PLL locked signal.
■ PLL reference clock frequency drifts outside the lock range specification.
Boolean
Device Support
You can use this setting in projects targeting the following device families:
■ Arria V
■ Cyclone V
■ Stratix V
Notes
This assignment supports wildcards.
This assignment is included in the Fitter report.
Syntax
set_instance_assignment -name PLL_AUTO_RESET -to -entity
Quartus Settings File June 2012 Altera Corporation
Reference Manual