Quartus II Settings File Reference Manual - Altera

6–92 Chapter 6: Fitter Assignments
DUAL_PURPOSE_CLOCK_PIN_DELAY
DUAL_PURPOSE_CLOCK_PIN_DELAY
Type
Specifies the propagation delay from a dual-purpose clock pin to its fan-out
destinations that are routed on the global clock network. Legal integer values range
from 0 through 63 for Cyclone and Cyclone II device families and from 0 through 11
for Cyclone III, where 0 is the setting with the least delay and 63 is the setting with the
most delay. This is an advanced option that should be used only after you have
compiled a project, checked the I/O timing, and determined that the timing is
unsatisfactory. For detailed information on how to use this option, refer to the data
sheet for the device family. This option is ignored if it is applied to anything other
than an input or bidirectional pin, or if the pin is user assigned to a non-dual-purpose
clock pin location.
Integer
Device Support
This setting can be used in projects targeting the following device families:
■ Cyclone
■ Cyclone II
■ Cyclone III
■ Cyclone III LS
■ Cyclone IV E
■ Cyclone IV GX
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name DUAL_PURPOSE_CLOCK_PIN_DELAY -to -
entity
Quartus Settings File June 2012 Altera Corporation
Reference Manual