Quartus II Settings File Reference Manual - Altera

6–16 Chapter 6: Fitter Assignments
AUTO_MERGE_PLLS
AUTO_MERGE_PLLS
Type
Allows the Compiler to automatically find and merge together two compatible phaselocked
loops (PLL) driven by the same clock source, reducing the total number of
PLLs used in a design.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ Arria GX
■ Arria II GX
■ Arria II GZ
■ Cyclone
■ Cyclone II
■ Cyclone III
■ Cyclone III LS
■ Cyclone IV E
■ Cyclone IV GX
■ HardCopy II
■ HardCopy III
■ HardCopy IV
■ Stratix
■ Stratix GX
■ Stratix II
■ Stratix II GX
■ Stratix III
■ Stratix IV
Notes
This assignment supports wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_MERGE_PLLS
set_global_assignment -name AUTO_MERGE_PLLS -entity
Quartus Settings File June 2012 Altera Corporation
Reference Manual