Quartus II Settings File Reference Manual - Altera

Chapter 6: Fitter Assignments 6–257
PLL_COMPENSATE
PLL_COMPENSATE
Type
Allows you to specify an output pin as a compensation target for a PLL in
ZERO_DELAY_BUFFER or EXTERNAL_FEEDBACK mode, or an input pin or a
group of input pins as compensation targets for a PLL in SOURCE_SYNCHRONOUS
mode. If assigned to an output pin, the pin must be fed by the external clock output
port of a PLL in a Stratix, Hardcopy Stratix or Cyclone device, or the compensated
clock output port of a PLL in other devices. Any other output pins fed by the same
PLL generally are not delay compensated, especially if they have different I/O
standards. If assigned to an input pin or a group of input pins, the input pins must
drive input registers that are clocked by the compensated clock output port of a PLL
in SOURCE_SYNCHRONOUS mode. This option is ignored if it is applied to
anything other than an output or input pin as described previously.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ Arria GX
■ Arria II GX
■ Arria II GZ
■ Arria V
■ Cyclone II
■ Cyclone III
■ Cyclone III LS
■ Cyclone IV E
■ Cyclone IV GX
■ Cyclone V
■ HardCopy II
■ HardCopy III
■ HardCopy IV
■ Stratix
■ Stratix GX
■ Stratix II
■ Stratix II GX
■ Stratix III
■ Stratix IV
■ Stratix V
June 2012 Altera Corporation Quartus Settings File
Reference Manual