Quartus II Settings File Reference Manual - Altera

4–186 Chapter 4: Analysis & Synthesis Assignments
SYNTH_TIMING_DRIVEN_SYNTHESIS
SYNTH_TIMING_DRIVEN_SYNTHESIS
Type
Allows the Quartus II Synthesis to use timing information during synthesis to
optimize the design.
When you turn this option on, the Quartus II Synthesis runs timing analysis to obtain
timing information about the netlist, and optimizes the netlist accordingly. It also
automatically applies the SDC Constraint Protection logic option.
You can use this option when regular synthesis does not optimize the circuit well for
the given timing constraints. When you set the Timing-Driven Synthesis option to
on, you can expect Synthesis to perform better at the cost of some ALUTs and/or
registers. Runtime and peak memory slightly increases as well.
This option can only be used for Cyclone II, Cyclone III, Cyclone III LS, Cyclone IV,
Arria II GX, Stratix II, HardCopy II, Stratix III, HardCopy III, Stratix IV and HardCopy
IV families. It is ignored for other families. It is also ignored when the Synthesis Effort
is set to Fast. Appropriate warnings are given when the option is ignored.
When you set this option to on, Altera recommends that you specify a device for the
design. If no device is specified, timing-driven synthesis automatically uses the
smallest device in the family that satisfies design constraints like speed grade and
package. It gives an error when no valid device can be found.
This option can be used as a project-wide option only.
This option defaults to Off.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ Arria GX
■ Arria II GX
■ Arria II GZ
■ Arria V
■ Cyclone II
■ Cyclone III
■ Cyclone III LS
■ Cyclone IV E
■ Cyclone IV GX
■ Cyclone V
■ HardCopy II
■ HardCopy III
■ HardCopy IV
Quartus Settings File June 2012 Altera Corporation
Reference Manual