Quartus II Settings File Reference Manual - Altera

Chapter 4: Analysis & Synthesis Assignments 4–179
SYNTH_GATED_CLOCK_CONVERSION
SYNTH_GATED_CLOCK_CONVERSION
Type
Automatically converts gated clocks in the design to use clock enable pins if clock
enable pins are not used in the original design. Clock gating logic can contain AND,
OR, MUX, and NOT gates. Turning on this option may increase memory use and
overall run time. You must use the TimeQuest Timing Analyzer for timing analysis,
and you must define all base clocks in Synopsys Design Constraints File (.sdc) format.
You can use this option for ASIC prototyping flow on FPGA, and only works with the
TimeQuest timing analyzer. For more information, refer to Quartus II Development
Software Handbook on the Altera website.
This option may cause memory usage and run time increase.
You can use this option as a project-wide option, or assigned to a design entity.
This option defaults to Off.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ Arria GX
■ Arria II GX
■ Arria II GZ
■ Arria V
■ Cyclone II
■ Cyclone III
■ Cyclone III LS
■ Cyclone IV E
■ Cyclone IV GX
■ Cyclone V
■ HardCopy II
■ HardCopy III
■ HardCopy IV
■ Stratix II
■ Stratix II GX
■ Stratix III
■ Stratix IV
■ Stratix V
June 2012 Altera Corporation Quartus Settings File
Reference Manual