Quartus II Settings File Reference Manual - Altera

4–20 Chapter 4: Analysis & Synthesis Assignments
AUTO_CLOCK_ENABLE_RECOGNITION
AUTO_CLOCK_ENABLE_RECOGNITION
Type
Allows the Compiler to find logic that feeds a register and move the logic to the
register’s clock enable input port.
This option can bet set to Off on individual registers or design entities to solve fitting
and performance issues with designs that have many clock enables generated by
Analysis & Synthesis.
This option is turned on by default.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ Arria GX
■ Arria II GX
■ Arria II GZ
■ Arria V
■ Cyclone
■ Cyclone II
■ Cyclone III
■ Cyclone III LS
■ Cyclone IV E
■ Cyclone IV GX
■ Cyclone V
■ HardCopy II
■ HardCopy III
■ HardCopy IV
■ MAX II
■ MAX V
■ Stratix
■ Stratix GX
■ Stratix II
■ Stratix II GX
■ Stratix III
■ Stratix IV
■ Stratix V
Quartus Settings File June 2012 Altera Corporation
Reference Manual