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Quartus II Settings File Reference Manual - Altera

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6–22 Chapter 6: Fitter Assignments<br />

AUTO_PACKED_REGISTERS_STRATIX<br />

AUTO_PACKED_REGISTERS_STRATIX<br />

Type<br />

Allows the Compiler to automatically implement a register and a combinational<br />

function in the same logic cell, or to implement registers using I/O cells, RAM blocks,<br />

or DSP blocks instead of logic cells. This option controls how aggressively the Fitter<br />

combines registers with other function blocks in order to reduce logic element count.<br />

If this option is set to Off, the Fitter does not attempt to place a pair of logic functions<br />

in a single logic cell; however, logic cells specified during synthesis to perform both a<br />

combinational and a sequential function are maintained. If this option is set to<br />

Normal, the Fitter places both a combinational and a sequential operation in a logic<br />

cell when it is expected that the placement does not affect design performance. When<br />

this option is set to Minimize Area, the Fitter aggressively combines unrelated<br />

sequential and combinational functions into a single logic cell in order to reduce the<br />

logic cell count, even at the expense of design performance. When this option is set to<br />

Minimize Area with Chains, the Fitter even more aggressively combines sequential<br />

and combinational functions that are part of arithmetic or register cascade chains or<br />

that can be converted to register cascade chains. When this setting is Auto, the fitter<br />

attempts to achieve the best performance while maintaining a fit for the design in the<br />

specified device. The Fitter combines all combinational and sequential functions that<br />

are deemed to benefit circuit speed. In addition, more aggressive combinations of<br />

unrelated combinational and sequential functions are performed to the extent<br />

required to reduce the area of the design in order to achieve a fit in the specified<br />

device. If this option is set to any value but Off, registers are merged with I/O cells to<br />

improve I/O timing, and with DSP blocks and RAM blocks to reduce logic cell count<br />

or improve timing when possible.<br />

Enumeration<br />

■ Auto<br />

■ Minimize Area<br />

■ Minimize Area with Chains<br />

■ Normal<br />

■ Off<br />

Device Support<br />

This setting can be used in projects targeting the following device families:<br />

■ Stratix<br />

■ Stratix GX<br />

Notes<br />

This assignment supports wildcards.<br />

This assignment is included in the Fitter report.<br />

Syntax<br />

set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX <br />

<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />

<strong>Reference</strong> <strong>Manual</strong>

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