Quartus II Settings File Reference Manual - Altera

Chapter 4: Analysis & Synthesis Assignments 4–193
VERILOG_CONSTANT_LOOP_LIMIT
VERILOG_CONSTANT_LOOP_LIMIT
Type
Defines the iteration limit for Verilog loops with loop conditions that evaluate to
compile-time constants on each loop iteration. For example, such loops would have
loop conditions that depend only on loop variables and constant expressions. If a loop
condition refers to an input to the current module or to another variable other than a
loop-variable, then the loop condition is most likely a non-constant loop condition,
which has a separate limit in the Quartus II software. This logic option exists
primarily to catch potential infinite loops before they exhaust memory or trap the
software in an actual infinite loop. In general, you should only increase the value of
this option, unless you are trying to identify a loop that requires excessive amounts of
logic and therefore exhausts the memory available to the Quartus II software. If you
decrease the value of this logic option, you may receive errors for loops that
previously passed synthesis.
This option can be used as a project-wide option, or assigned to a design entity.
This option defaults to 5000.
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -entity
set_instance_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -to -entity
Example
set_global_assignment -name verilog_constant_loop_limit 3000
Default Value
5000
June 2012 Altera Corporation Quartus Settings File
Reference Manual