Quartus II Settings File Reference Manual - Altera

6–230 Chapter 6: Fitter Assignments
OUTPUT_PIN_LOAD
OUTPUT_PIN_LOAD
Type
Specifies the capacitive load, in picofarads (pF), on output pins for each I/O standard.
These settings affect FPGA pins only. To specify board trace, termination, and
capacitive load parameters for use with Advanced I/O Timing, use the Board Trace
Model tab. Capacitive loading is ignored if applied to anything other than an output
or bidirectional pin, or if Advanced I/O Timing is enabled.
Integer
Device Support
The value must be between these two numbers, inclusive: 0, 10000
This setting can be used in projects targeting the following device families:
■ Arria GX
■ Cyclone
■ Cyclone II
■ HardCopy II
■ MAX II
■ MAX V
■ MAX3000A
■ MAX7000A
■ MAX7000AE
■ MAX7000B
■ Stratix
■ Stratix GX
■ Stratix II
■ Stratix II GX
Notes
This assignment is copied to any duplicated nodes
Syntax
set_instance_assignment -name OUTPUT_PIN_LOAD -to -entity
set_global_assignment -name OUTPUT_PIN_LOAD -section_id
Quartus Settings File June 2012 Altera Corporation
Reference Manual