Quartus II Settings File Reference Manual - Altera

4–146 Chapter 4: Analysis & Synthesis Assignments
REMOVE_REDUNDANT_LOGIC_CELLS
REMOVE_REDUNDANT_LOGIC_CELLS
Type
Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option
on optimizes a circuit for area and speed. This option is ignored if it is applied to
anything other than a design entity.
This option defaults to Off.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ Arria GX
■ Arria II GX
■ Arria II GZ
■ Arria V
■ Cyclone
■ Cyclone II
■ Cyclone III
■ Cyclone III LS
■ Cyclone IV E
■ Cyclone IV GX
■ Cyclone V
■ HardCopy II
■ HardCopy III
■ HardCopy IV
■ MAX II
■ MAX V
■ Stratix
■ Stratix GX
■ Stratix II
■ Stratix II GX
■ Stratix III
■ Stratix IV
■ Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
Quartus Settings File June 2012 Altera Corporation
Reference Manual