Quartus II Settings File Reference Manual - Altera

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4–74 Chapter 4: Analysis & Synthesis Assignments EXTRACT_VHDL_STATE_MACHINES EXTRACT_VHDL_STATE_MACHINES Type Allows the Compiler to extract state machines from VHDL Design Files (.vhd). The Compiler optimizes state machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler extracts and optimizes state machines in VHDL Design Files (.vhd) as regular logic. This option is useful for preventing automatic state machine optimizations to manually optimized logic. This option can be used as a project-wide option only. This option is turned on by default. Boolean Device Support This setting can be used in projects targeting any Altera device family. Notes This assignment is included in the Analysis & Synthesis report. Syntax set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES Example set_global_assignment -name extract_vhdl_state_machines off Default Value On See Also ■ “STATE_MACHINE_PROCESSING” on page 4–158 ■ “EXTRACT_VERILOG_STATE_MACHINES” on page 4–73 Quartus Settings File June 2012 Altera Corporation Reference Manual
Chapter 4: Analysis & Synthesis Assignments 4–75 FAMILY FAMILY Type Specifies the device family to use for compilation. String Device Support This setting can be used in projects targeting any Altera device family. C Notes The value of this assignment is case sensitive. This assignment is included in the Fitter report. Syntax set_global_assignment -name FAMILY Default Value Cyclone IV GX June 2012 Altera Corporation Quartus Settings File Reference Manual
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Contents Chapter 1. Project-Wide As
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Contents iii TEMPLATE_FILE . . . .
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Contents v IGNORE_TRANSLATE_OFF_AND
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Contents vii Chapter 6. Fitter Assi
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Contents ix FLEX10K_MAX_PERIPHERAL_
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Contents xi PLL_FORCE_OUTPUT_COUNTE
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Contents xiii XCVR_GT_TX_PRE_EMP_PR
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Contents xv VCCA_R_USER_VOLTAGE . .
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Contents xvii EDA_WRITER_DONT_WRITE
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Revision History © 2012 Altera Cor
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Appendix : About-3 Assignment Value
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Appendix : About-5 Overview Overvie
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