Quartus II Settings File Reference Manual - Altera

Chapter 4: Analysis & Synthesis Assignments 4–93
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
Type
Instructs Analysis & Synthesis to ignore all translate_off or synthesis_off
synthesis directives in your Verilog and VHDL design files. You can use this option to
disable these synthesis directives and include previously ignored code during
elaboration.
You can use this option to compile code that was previously ignored by third-party
synthesis tools, for example, megafunction declarations that were treated as blackboxes
in other tools but that may be compiled in the Quartus II software.
This option defaults to Off.
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
Example
set_global_assignment -name ignore_translate_off_and_synthesis_off on
Default Value
Off
June 2012 Altera Corporation Quartus Settings File
Reference Manual