Quartus II Settings File Reference Manual - Altera

Chapter 6: Fitter Assignments 6–267
PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING
Type
Allows the Fitter to set the phase shift of a PLL output counter, and hence the phase
shift of its generated clock, to improve timing for all edges affected by this clock.
Apply multicycle timing exceptions to paths between the generated clock and other
clocks in the design to avoid timing violations.
Boolean
Device Support
This setting can be used in projects targeting the following device families:
■ Arria V
■ Cyclone V
■ Stratix V
Notes
This assignment supports wildcards.
This assignment is included in the Fitter report.
Syntax
set_instance_assignment -name PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING -to
-entity
June 2012 Altera Corporation Quartus Settings File
Reference Manual