Quartus II Settings File Reference Manual - Altera

4–74 Chapter 4: Analysis & Synthesis Assignments
EXTRACT_VHDL_STATE_MACHINES
EXTRACT_VHDL_STATE_MACHINES
Type
Allows the Compiler to extract state machines from VHDL Design Files (.vhd). The
Compiler optimizes state machines using special techniques to reduce area and/or
improve performance. If set to Off, the Compiler extracts and optimizes state
machines in VHDL Design Files (.vhd) as regular logic.
This option is useful for preventing automatic state machine optimizations to
manually optimized logic.
This option can be used as a project-wide option only.
This option is turned on by default.
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES
Example
set_global_assignment -name extract_vhdl_state_machines off
Default Value
On
See Also
■ “STATE_MACHINE_PROCESSING” on page 4–158
■ “EXTRACT_VERILOG_STATE_MACHINES” on page 4–73
Quartus Settings File June 2012 Altera Corporation
Reference Manual