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Quartus II Settings File Reference Manual - Altera

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6–24 Chapter 6: Fitter Assignments<br />

AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong><br />

AUTO_PACKED_REGISTERS_STRATIX<strong>II</strong><br />

Type<br />

Allows the Compiler to combine a register and a combinational function, or to<br />

implement registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells.<br />

This option controls how aggressively the Fitter combines registers with other<br />

function blocks to reduce the area of the design. Generally, the Auto or Sparse Auto<br />

settings should be used for this option. The other options limit the flexibility of the<br />

Fitter to combine registers with other function blocks and can result in no fits. When<br />

Auto, the default setting is selected, the Fitter attempts to achieve the best<br />

performance with good area. If necessary, additional logic is combined to reduce the<br />

area of the design so that it can fit within the selected device. When this setting is<br />

Sparse Auto, the Fitter attempts to achieve the highest performance with possibly<br />

increased area, but without exceeding the logic capacity of the device. If this option is<br />

set to Off, the Fitter does not combine registers with other functions. The Off setting<br />

severely increases the area of the design and may cause a no fit. If this option is set to<br />

Sparse, the Fitter combines functions in a way which improves performance for many<br />

designs. If this option is set to Normal, the Fitter combines functions that are expected<br />

to maximize design performance and reduce area. When this option is set to<br />

Minimize Area, the Fitter aggressively combines unrelated functions to reduce the<br />

area required for placing the design, at the expense of performance. When this option<br />

is set to Minimize Area with Chains, the Fitter even more aggressively combines<br />

functions that are part of register cascade chains or can be converted to register<br />

cascade chains. If this option is set to any value but Off, registers are combined with<br />

I/O cells to improve I/O timing (as long as the Optimize IOC Register Placement<br />

For Timing option allows it), and with DSP blocks and RAM blocks to reduce the area<br />

required for placing the design or to improve timing when possible.<br />

Enumeration<br />

■ Auto<br />

■ Minimize Area<br />

■ Minimize Area with Chains<br />

■ Normal<br />

■ Off<br />

■ Sparse<br />

■ Sparse Auto<br />

Device Support<br />

This setting can be used in projects targeting the following device families:<br />

■ Arria GX<br />

■ Arria <strong>II</strong> GX<br />

■ Arria <strong>II</strong> GZ<br />

■ Arria V<br />

■ Cyclone <strong>II</strong><br />

<strong>Quartus</strong> <strong>Settings</strong> <strong>File</strong> June 2012 <strong>Altera</strong> Corporation<br />

<strong>Reference</strong> <strong>Manual</strong>

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