Quartus II Settings File Reference Manual - Altera

Chapter 6: Fitter Assignments 6–259
PLL_COMPENSATION_MODE
PLL_COMPENSATION_MODE
Specifies the routing path of the PLL feedback clock and adjusts the delay chains in
the PLL.
■ Direct—The aim of this setting is to produce the smallest possible jitter at the PLL
output. You can perform this by minimizing the length of the feedback path by not
compensating for anything.
■ External Feedback—The goal is to have the clock edge at the clock output pin to
occur earlier than the clock edge at the clock input (reference) pin, by the amount
of board trace delay placed between the clock output pin and the external
feedback input pin. In this mode what needs to be compensated for within the
FPGA is any difference in delay between the two paths:
■ Clock Input Pin to the PLL PFD input
■ External Feedback Input Pin to the PLL PFD input
■ LVDS—The aim of this setting is to maintain the same data and clock timing
relationship seen at the pins at the internal SERDES capture register. Thus, this
mode ideally compensates for the delay of the LVDS clock network, plus any
differences in delay between the following two paths:
■ Data Pin to SERDES capture register
■ Clock Input Pin to SERDES capture register
The compensation mimic path is designed to mimic the clock and data delay of the
receiver side.
■ Normal—The aim of this setting is to have the clock edge at an IOE or LE register
to occur at the same time that it does at the Clock Input Pin. Thus, this mode
ideally compensates for the clock network used and the delay from the Clock
Input Pin to the PLL PFD input. Since you are unable to compensate for the delay
in the first stage of the input buffer, you must use a delay chain for compensation.
■ Source Synchronous—The aim of this setting is to maintain the same data and
clock timing relationship seen at the pins at any IOE register. Thus, this mode
ideally compensates for the delay of the clock network used, including any
differences in delay between the following two paths:
■ Data Pin to IOE register input
■ Clock Input Pin to PLL PFD input
There is a delay cell block in the feedback path to compensate for the timing
differences between the SE and DIFF input delay in the IO register and wire delay.
■ Zero Delay Buffer—The goal is to have zero delay between a clock edge at the
clock input pin and the clock output pin. This consumes a clock output pin to
provide the output buffer delay compensation. Thus this mode ideally
compensates for the delay from the clock input pin to the PLL PFD input, plus the
delay from the PLL output to the clock output pin.
If the input clock and feedback buffers use different IO standard, we need to
compensate the delay different by using delay chain.
June 2012 Altera Corporation Quartus Settings File
Reference Manual