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NUMERICAL SIMULATIONS OF CRYSTAL GROWTH TECHNIQUES 249<br />

Liquid<br />

Solid<br />

Convex<br />

Liquid<br />

Solid<br />

Concave<br />

>1600<br />

>1460<br />

>1320<br />

>1180<br />

>1040<br />

>900<br />

>760<br />

>620<br />

>480<br />

>340<br />

>200<br />

[°C]<br />

Figure 6.30 Examples of convex and concave liquid–solid interfaces due to the variation of side<br />

wall heating power. Both pictures are taken at the same process time<br />

Liquid<br />

Solid<br />

Top of<br />

ingot<br />

Region<br />

of<br />

enclosed<br />

melt<br />

Solidified<br />

silicon<br />

>1600<br />

>1460<br />

>1320<br />

>1180<br />

>1040<br />

>900<br />

>760<br />

>620<br />

>480<br />

>340<br />

>200<br />

[°C]<br />

Figure 6.31 Simulation result representing a remarkable decrease of heating power at the top<br />

region of the ingot. By this, the solidification time is reduced to half, but solidification ends with<br />

an inclusion of silicon melt<br />

the furnace operator to find the balance between material quality, which is known to be<br />

high in the case of planar solidification, and process economy.<br />

In Figure 6.31, simulation results are shown, representing a noticeable reduction<br />

of heating power at the ingot top. By this, the solidification velocity can be speeded up<br />

and the time for solidification is reduced to half. However, in the simulated case study,<br />

the solidification ends with an encapsulation of the melt by solidified silicon. Because<br />

of the 10% higher density of liquid silicon with respect to the solid phase, this process<br />

scenario causes a burst out of melt from ingots volume. This can lead to a crack in the<br />

mould and to a damage of the furnace. These case-study simulations can find worst-case<br />

process conditions that must be avoided in production. For more simulation results of the<br />

SOPLIN process, see [92–94].<br />

6.6.4 Simulation of Silicon Ribbon Growth<br />

As a second example of silicon crystallisation processes, the RGS is taken. The basic idea<br />

of this process is the de-coupling of the pulling direction of substrates on which silicon

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