PCT/1998/43 - World Intellectual Property Organization

43/1998
29 Oct/oct 1998 PCT Gazette - Section I - Gazette du PCT 15093
(22) 21 Apr/avr 1998 (21.04.1998)
(25) ja (26) ja
(31) 9/103716 (32) 21 Apr/avr 1997
(21.04.1997)
(31) 9/103717 (32) 21 Apr/avr 1997
(21.04.1997)
(33) JP
(33) JP
(43) 29 Oct/oct 1998 (29.10.1998)
(51) 6 H01L 21/60
(54) • INTERELECTRODE CONNECTING STRUC-
TURE, INTERELECTRODE CONNECTING
METHOD, SEMICONDUCTOR DEVICE,
SEMICONDUCTOR MOUNTING METHOD,
LIQUID CRYSTAL DEVICE, AND ELEC-
TRONIC EQUIPMENT
•
STRUCTURE ET PROCEDE DE CONNEXION
ENTRE ELECTRODES, DISPOSITIF A SEMI–
CONDUCTEUR, PROCEDE DE MONTAGE
DE SEMI–CONDUCTEUR, DISPOSITIF A
CRISTAUX LIQUIDES ET MATERIEL ELEC-
TRONIQUE
(71) SEIKO EPSON CORPORATION [JP/JP]; 4–1,
Nishi–shinjuku 2–chome, Shinjuku–ku, Tokyo
163–0811 (JP).
(for all designated States except / pour tous les États
désignés sauf US)
(72, 75) UCHIYAMA, Kenji [JP/JP]; Seiko Epson
Corporation, 3–5, Owa 3–chome, Suwa–shi, Nagano–ken
392–8502 (JP).
(74) SUZUKI, Kisaburo et al. / etc.; Seiko Epson
Corporation, Intellectual Property Dept., 3–5, Owa
3–chome, Suwa–shi, Nagano–ken 392–8502 (JP).
(81) CN JP KR US.
(11) WO 98/48456 (13) A1
(21) PCT/US98/08098
(22) 22 Apr/avr 1998 (22.04.1998)
(25) en (26) en
(31) 60/044,008 (32) 24 Apr/avr 1997
(24.04.1997)
(33) US
(43) 29 Oct/oct 1998 (29.10.1998)
(51) 6 H01L 21/768, 21/311
(54) • NANOWIRE ARRAYS
• MATRICES DE NANOFILS
(71) MASSACHUSETTS INSTITUTE OF
TECHNOLOGY [US/US]; 77 Massachusetts
Avenue, Cambridge, MA 02139 (US).
(72) YING, Jackie, Y.; 9 Fairlane Terrace, Winchester,
MA 01890 (US). ZHANG, Zhibo; Apartment
#1, 3 Prentiss Street, Cambridge, MA 02140 (US).
ZHANG, Lei; Room 205, 350 Memorial Drive,
Cambridge, MA 02139 (US). DRESSELHAUS,
Mildred, S.; 147 Jason Street, Arlington, MA
02176 (US).
(74) DALY, Christopher, S. et al. / etc.; Nutter,
McClennen & Fish, LLP, One International Place,
Boston, MA 02110 (US).
(81) CA JP; EP (AT BE CH CY DE DK ES FI FR GB
GR IE IT LU MC NL PT SE).
(11) WO 98/48457 (13) A1
(21) PCT/US98/05516
(22) 19 Mar/mar 1998 (19.03.1998)
(25) en (26) en
(31) 08/844,924 (32) 21 Apr/avr 1997
(21.04.1997)
(33) US
(43) 29 Oct/oct 1998 (29.10.1998)
(51) 6 H01L 21/8238
(54) • METHOD OF MAKING NMOS AND PMOS
DEVICES WITH REDUCED MASKING
STEPS
• PROCEDE DE FABRICATION DE DISPOSI-
TIFS NMOS ET PMOS NECESSITANT UN
NOMBRE REDUIT D’ETAPES DE MAS-
QUAGE
(71) ADVANCED MICRO DEVICES, INC. [US/US];
One AMD Place, Mail Stop 68, Sunnyvale, CA
94088–3453 (US).
(72) HAUSE, Frederick, N.; 4702 Circle Oak Cove,
Austin, TX 78749 (US). DAWSON, Robert;
3504 Beartree Circle, Austin, TX 78730 (US).
FULFORD, H., Jim; 9808 Woodshire Drive,
Austin, TX 78748 (US). GARDNER, Mark,
I.; Highway 535, P.O. Box 249, Cedar Creek,
TX 78612 (US). MICHAEL, Mark, W.; 1805
Dayflower Trace, Cedar Park, TX 78613 (US).
MOORE, Bradley, T.; 1502 Johnny Miller Trail,
Austin, TX 78746 (US). WRISTERS, Derick, J.;
1904 Terish Cover, Austin, TX 78728 (US).
(74) DRAKE, Paul, S.; Advanced Micro Devices, Inc.,
5204 East Ben White Boulevard, M/S 562, Austin,
TX 78741 (US).
(81) JP KR; EP (AT BE CH DE DK ES FI FR GB GR
IE IT LU MC NL PT SE).
(11) WO 98/48458 (13) A1
(21) PCT/US98/08112
(22) 20 Apr/avr 1998 (20.04.1998)
(25) en (26) en
(31) 08/837,685 (32) 21 Apr/avr 1997 (33) US
(21.04.1997)
(43) 29 Oct/oct 1998 (29.10.1998)
(51) 6 H01L 23/48, 23/52, 29/40
(54) • BALL GRID ARRAY PACKAGE EM-
PLOYING SOLID CORE SOLDER BALLS
• BOITIER A MATRICE DE GRILLE UTILI-
SANT DES BILLES DE SOUDURE A NOYAU
SOLIDE
(71) LSI LOGIC CORPORATION [US/US]; 1551
McCarthy Boulevard, Milpitas, CA 95035 (US).
(for all designated States except / pour tous les États
désignés sauf US)
(72, 75) CHIA, Chok, J. [MY/US]; 10132 Prado Vista
Drive, Cupertino, CA 95014 (US). VARIOT, Patrick
[FR/US]; 2445 Westgate Avenue, San Jose,
CA 95125 (US). ALAGARATNAM, Maniam
[US/US]; 10424 Dempster Avenue, Cupertino, CA
95014 (US).
(74) WOODWARD, Henry, K. et al. / etc.; Townsend
and Townsend and Crew LLP, 8th floor, Two Embarcadero
Center, San Francisco, CA 94111–3834
(US).
(81) AL AM AT AU AZ BA BB BG BR BY CA CH
CN CU CZ DE DK EE ES FI GB GE GH GM GW
HU ID IL IS JP KE KG KP KR KZ LC LK LR
LS LT LU LV MD MG MK MN MW MX NO NZ
PL PT RO RU SD SE SG SI SK SL TJ TM TR
TT UA UG US UZ VN YU ZW; AP (GH GM KE
LS MW SD SZ UG ZW); EA (AM AZ BY KG
KZ MD RU TJ TM); EP (AT BE CH CY DE DK
ES FI FR GB GR IE IT LU MC NL PT SE); OA
(BF BJ CF CG CI CM GA GN ML MR NE SN
TD TG).
(11) WO 98/48459 (13) A1
(21) PCT/DE98/00769
(22) 13 Mar/mar 1998 (13.03.1998)
(25) de (26) de
(31) 197 16 102.2 (32) 17 Apr/avr 1997 (33) DE
(17.04.1997)
(43) 29 Oct/oct 1998 (29.10.1998)
(51) 6 H01L 23/60, 27/06
(54) • INTEGRATED CIRCUIT WITH SEVERAL
COMPONENTS AND METHOD FOR THE
PRODUCTION THEREOF
• CIRCUIT INTEGRE A PLUSIEURS COMPO-
SANTS ET SON PROCEDE DE PRODUC-
TION
(71) SIEMENS AKTIENGESELLSCHAFT
[DE/DE]; Wittelsbacher Platz 2, D–80333
München (DE).
(for all designated States except / pour tous les États
désignés sauf US)
(72, 75) ANTHOFER, Anton [DE/DE]; Böcklmühle
26, D–92271 Freihung (DE). HÜBNER, Holger
[DE/DE]; Hamsterweg 10, D–85598 Baldham
(DE).
(81) JP KR US; EP (AT BE CH DE DK ES FI FR GB
GR IE IT LU MC NL PT SE).
Published / Publiée : (c)
(11) WO 98/48460
(21) PCT/US98/07945
(13) A1
(22) 20 Apr/avr 1998 (20.04.1998)
(25) en (26) en
(31) 08/842,230 (32) 22 Apr/avr 1997
(22.04.1997)
(33) US
(43) 29 Oct/oct 1998 (29.10.1998)
(51) 6 H01L 27/108
(54) • MEMORY INTEGRATED CIRCUITRY
• CIRCUIT INTEGRE DE MEMOIRE
(71) MICRON TECHNOLOGY, INC. [US/US]; 8000
South Federal Way, Boise, ID 83706–9632 (US).
(72) TRAN, Luan, C.; 1125 W. Sandy Court, Meridian,
ID 83652 (US). REINBERG, Alan, R.; 1910 Lake
Heron Lane, Boise, ID 83706 (US).
(74) MATKIN, Mark, S. et al. / etc.; Wells, St. John,
Roberts, Gregory & Matkin, P.S., W. 601 First
Avenue #1300, Spokane, WA 99201–3817 (US).
(81) AL AM AT AU AZ BA BB BG BR BY CA CH
CN CU CZ DE DK EE ES FI GB GE GH GM
GW HU ID IL IS JP KE KG KP KR KZ LC LK
LR LS LT LU LV MD MG MK MN MW MX NO
NZ PL PT RO RU SD SE SG SI SK SL TJ TM
TR TT UA UG UZ VN YU ZW; AP (GH GM KE
LS MW SD SZ UG ZW); EA (AM AZ BY KG
KZ MD RU TJ TM); EP (AT BE CH CY DE DK
ES FI FR GB GR IE IT LU MC NL PT SE); OA
(BF BJ CF CG CI CM GA GN ML MR NE SN
TD TG).
Published / Publiée : (c)
(11) WO 98/48461
(21) PCT/US98/06873
(13) A1
(22) 9 Apr/avr 1998 (09.04.1998)
(25) en (26) en
(31) 08/844,536 (32) 18 Apr/avr 1997
(18.04.1997)
(33) US
(43) 29 Oct/oct 1998 (29.10.1998)
(51) 6 H01L 31/0203, 23/10, G11C 16/00
(54) • INTEGRATED CIRCUIT PACKAGE
• BOITIER DE MICROCIRCUIT