80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNITT1 T2 T3 T4CLKOUTS2:0Status ValidALEA19:16BHE[A15:8]AD15:0[AD7:0]Address ValidAddressValidA18:16 = 0, A19=Valid StatusValidData ValidWRDT/RDENA1085-0AFigure 3-21. Typical Write Bus CycleTable 3-4. Write Bus Cycle TypesStatus BitsS2 S1 S0Bus Cycle Type0 1 0 Write I/O — Initiated by executing IN, OUT, INS, OUTS instructions. A15:0select the desired I/O port. A19:16 are driven to zero (see Chapter 10, “DirectMemory Access Unit”).1 1 0 Write Memory —Initiated by any of the Byte/ Word memory instructions. A19:0selects the desired byte or word memory location.Figure 3-22 illustrates a typical 16-bit interface connection to a read/write device. Write bus cycleshave many parameters that must be evaluated in determining the compatibility of a memory(or I/O) device. Table 3-5 lists some critical write bus cycle parameters.3-23