80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNITCLKOUTHOLD12345HLDAAD15:0DENRD, WR, BHE,DT / R, S2:0,A19:16NOTES:1. TCLIS: HOLD recognition setup to clock low2. : HOLD internally synchronized3. TCLOV: Clock low to HLDA low4. TCHOV: Clock high to signal active (high or low)5. TCLOV: Clock low to signal active (high or low)A1099-0AFigure 3-36. Exiting HOLD3.8 BUS CYCLE PRIORITIESThe BIU arbitrates requests for bus cycles from the Execution Unit, the integrated peripherals(e.g., Interrupt Control Unit) and external bus masters (i.e., bus hold requests). The list belowsummarizes the priorities for all bus cycle requests (from highest to lowest).1. Instruction execution read/write following a non-pipelined effective address calculation.2. Refresh bus cycles.3. Bus hold request.4. Single step interrupt vectoring sequence.5. Non-Maskable interrupt vectoring sequence.3-44