80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1.10 Stack ImplementationStacks in the 80C186 Modular Core family reside in memory space. They are located by the StackSegment register (SS) and the Stack Pointer (SP). A system can have multiple stacks, but onlyone stack is directly addressable at a time. A stack can be up to 64 Kbytes long, the maximumlength of a segment. Growing a stack segment beyond 64 Kbytes overwrites the beginning of thesegment. The SS register contains the base address of the current stack. The top of the stack, notthe base address, is the origination point of the stack. The SP register contains an offset that pointsto the Top of Stack (TOS).Stacks are 16 bits wide. Instructions operating on a stack add and remove stack elements oneword at a time. An element is pushed onto the stack (see Figure 2-10) by first decrementing theSP register by 2 and then writing the data word. An element is popped off the stack by copyingit from the top of the stack and then incrementing the SP register by 2. The stack grows down inmemory toward its base address. Stack operations never move or erase elements on the stack. Thetop of the stack changes only as a result of updating the stack pointer.2.1.11 Reserved Memory and I/O SpaceTwo specific areas in memory and one area in I/O space are reserved in the 80C186 Core family.• Locations 0H through 3FFH in low memory are used for the Interrupt Vector Table.Programs should not be loaded here.• Locations 0FFFF0H through 0FFFFFH in high memory are used for system reset codebecause the processor begins execution at 0FFFF0H.• Locations 0F8H through 0FFH in I/O space are reserved for communication with other Intelhardware products and must not be used. On the 80C186 core, these addresses are used asI/O ports for the 80C187 numerics processor extension.2-15
OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREExistingStackPUSH AX12 34POP AXPOP BX10 50BBAA1062001110620011106200111060105E105B105ATOS1058105610541052105022446688AA014589CD33557799BB2367ABEFBottom of stackNot presentlyon stack1060105E105B105A1058TOS105610541052105022446688AA344589CD33557799BB1267ABEF1060105E105BTOS105A1058105610541052105022446688AA344589CD33557799BB1267ABEF10 50SS10 50SS10 50SS00 08SP00 06SP00 0ASPStack operation for code sequencePUSH AXPOP AXPOP BXA1013-0AFigure 2-10. Stack Operation2-16
Page 1 and 2: 80C186EB/80C188EBMicroprocessorUser
Page 3 and 4: Information in this document is pro
Page 5 and 6: CONTENTS2.3.2 Software Interrupts .
Page 7 and 8: CONTENTS6.4.4 Enabling and Disablin
Page 9 and 10: CONTENTS10.2.2 Asynchronous Mode Pr
Page 11 and 12: CONTENTSFIGURESFigurePage2-1 Simpli
Page 13 and 14: CONTENTSFIGURESFigurePage6-9 Using
Page 15 and 16: CONTENTSTableTABLESPage1-1 Comparis
Page 17 and 18: CONTENTSEXAMPLESExamplePage5-1 Init
Page 20 and 21: CHAPTER 1INTRODUCTIONThe 8086 micro
Page 22 and 23: INTRODUCTIONEach chapter covers a s
Page 24 and 25: INTRODUCTION1.3.1 How to Use Intel'
Page 26: Overview of the80C186 FamilyArchite
Page 29 and 30: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 39: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 78: Bus Interface Unit3
Page 81 and 82: BUS INTERFACE UNITPhysical Implemen
Page 83 and 84: BUS INTERFACE UNIT(X + 1)(X)A19:1 D
Page 85 and 86: BUS INTERFACE UNITFor word transfer
Page 87 and 88: BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
Page 89 and 90: BUS INTERFACE UNITCLKOUTT4or TI T1
Page 91 and 92: BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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