80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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INDEXSHR instruction, A-9SI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32,2-34Sign Flag (SF), 2-7, 2-9Single-step trap (Type 1 exception), 2-43Softwarecode example80C187 floating-point routine, 12-1680C187 initialization, 12-13–12-15digital one-shot, 9-17–9-23I/O port configuration, 11-12ICU initialization, 8-24real-time clock, 9-17–9-19SCU asynchronous mode, 10-24SCU master/slave network, 10-28–10-36initialization code, 10-30–10-32_select_slave routine, 10-31–10-32_send_slave_command routine,10-36_slave_1 routine, 10-33–10-35SCU synchronous mode, 10-27square-wave generator, 9-17–9-22TCU configurations, 9-17–9-23data types, 2-37, 2-38dynamic code relocation, 2-13, 2-14interrupts, 2-45overview, 2-17See also Addressing modes, Instruction setSquare-wave generator, code example, 9-17–9-22SS register, 2-1, 2-5, 2-6, 2-13, 2-15, 2-30, 2-45Stack frame pointers, A-2Stack Pointer, 2-1, 2-5, 2-13, 2-15, 2-45Stack segment, 2-5Stacks, 2-15START registers, CSU, 6-5, 6-7, 6-11STOP registers, CSU, 6-5, 6-8, 6-12String instructions, 2-22–2-23and addressing modes, 2-34and memory-mapped I/O ports, 2-36operand locations, 2-13operands, 2-36Stringsaccessing, 2-13, 2-34defined, 2-37Synchronizing asynchronous inputs, B-1TTemporary real, defined, 12-7Terminology"above" vs "greater", 2-26"below" vs "less", 2-26device names, 1-2Timer Control Registers (TxCON), 9-7, 9-8Timer Count Registers (TxCNT), 9-10Timer Counter Unit (TCU), 9-1–9-23application examples, 9-17–9-23block diagram, 9-2clock sources, 9-12configuring a digital one-shot, 9-17–9-23configuring a real-time clock, 9-17–9-19configuring a square-wave generator, 9-17–9-22counting sequence, 9-12–9-13dual maxcount mode, 9-13–9-14enabling and disabling counters, 9-15–9-16frequency, maximum, 9-17initializing, 9-11input synchronization, 9-17interrupts, 9-16overview, 9-1–9-6programming, 9-6–9-16considerations, 9-16pulsed output, 9-14–9-15retriggering, 9-13–9-14setup and hold times, 9-16single maxcount mode, 9-13, 9-14–9-16timer delay, 9-1timing, 9-1and BIU, 9-1considerations, 9-16TxOUT signal, 9-15variable duty cycle output, 9-14–9-15Timer Maxcount Compare Registers (TxCMPA,TxCMPB), 9-11Timers‚ See Timer/Counter Unit (TCU), WatchdogtimerTrap exceptions, 2-43Trap Flag (TF), 2-7, 2-9, 2-43, 2-48T-stateand bus cycles, 3-9and CLKOUT, 3-8defined, 3-7Index-7
INDEXWWait statesand bus cycles, 3-13and chip-selects, 6-11–6-14and DRAM controllers, 7-1and PCB accesses, 4-4and READY input, 3-13Word integer, defined, 12-7Write bus cycle, 3-22ZZero Flag (ZF), 2-7, 2-9, 2-23Index-8
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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Page 369 and 370: INSTRUCTION SET DESCRIPTIONSTable C
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Page 390 and 391: APPENDIX DINSTRUCTION SET OPCODESAN
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Page 412: Index
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Page 419: INDEXblock diagram, 3-15implementat
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