80C186EB/80C188EB Microprocessor User's Manual - CEUNES

CHIP-SELECT UNIT$ TITLE (Chip-Select Unit Initialization)$ MOD186XREFNAMECSU_EXAMPLE_1; External reference from this module$ include(PCBMAP.INC) ;File declares Register;Locations and names.; Module equates; Configuration equatesTRUE EQU 0FFHFALSE EQU NOT TRUEREADY EQU 0001H ;Bus ready control modifierCSEN EQU 0008H ;Chip-Select enable modifierISTOP EQU 0004H ;Stop address modifierMEM EQU 0002H ;Memory select modifierIO EQU 0000H ;I/O select modifier;Below is a list of the default system memory and I/O environment. These;defaults configure the Chip-Select Unit for proper system operation.;EPROM memory is located from 0E0000 to 0FFFFF (128 Kbytes).;Wait states are calculated assuming 16MHz operation.;UCS# controls the accesses to EPROM memory space.EPROM_SIZEEQU 128 ;Size in KbytesEPROM_BASEEQU 1024 - EPROM_SIZE;Start address in KbytesEPROM_WAITEQU 1 ;Wait states;The UCS# START and STOP register values are calculated using the above system;constraints and the equations below.UCSST_VALEQUUCSSP_VALEQU(EPROM_BASE SHL 6) OR (EPROM_WAIT)(CSEN) OR (ISTOP) OR (MEM);SRAM memory starts at 0H and continues to 7FFFH (32 Kbytes).;Wait states are calculated assuming 16MHz operation.;LCS# controls the accesses to SRAM memory space.SRAM_SIZEEQU 32 ;Size in KbytesSRAM_BASEEQU 0 ;Start address in KbytesSRAM_WAITEQU 0 ;Wait states;The LCS# START and STOP register values are calculated using the above system;constraints and the equations below&LCSST_VALEQULCSSP_VALEQU(SRAM_BASE SHL 6) OR (SRAM_WAIT)(((SRAM_BASE) OR (SRAM_SIZE)) SHL 6) OR(CSEN) OR (MEM);A DRAM interface is selected by the GCS1# chip-select. The BASE value defines;the starting address of the DRAM window.The SIZE value (along with the BASE;value) defines the ending address. Zero wait state performance is assumed. The;Refresh Control Unit uses DRAM_BASE to properly configure refresh operation.Example 6-1. Initializing the Chip-Select Unit6-17