80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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BUS INTERFACE UNITT1 T2 T3 TW TW T4CLKOUTALES2:0ValidA19:16AddressAD15:0AddressValid Write DataWRREADYA1040-0AFigure 3-13. Typical Bus Cycle with Wait StatesREADYDQDQBUS READYCLKOUTRisingEdgeFallingEdgeA1079-01Figure 3-14. READY Pin Block Diagram3-15
BUS INTERFACE UNITA normally not-ready system is one in which READY remains low at all times except to signal aready condition. For any bus cycle, only the selected device drives the READY input high tocomplete the bus cycle. The circuit shown in Figure 3-15 illustrates a simple circuit to generate anormally not-ready signal. Note that if no device is selected the bus remains not-ready indefinitely.Systems with many slow devices that cannot operate at the maximum bus bandwidth usuallyimplement a normally not-ready signal.The start of a bus cycle clears the wait state module and forces READY low. After every risingedge of CLKOUT, INPUT1 and INPUT2 are shifted through the module and eventually driveREADY high. Assuming INPUT1 and INPUT2 are valid prior to phase 2 of T2, no delay throughthe module causes one wait state. Each additional clock delay through the module generates oneadditional wait state. Two inputs are used to establish different wait state conditions.CS1CS2CS3CS4Wait State ModuleInput 1Input 2OutREADYALECLKOUTClearClockA1080-0AFigure 3-15. Generating a Normally Not-Ready Bus SignalA normally ready signal remains high at all times except when the selected device needs to signala not-ready condition. For any bus cycle, only the selected device drives the READY input lowto delay the completion of the bus cycle. The circuit shown in Figure 3-16 illustrates a simple circuitto generate a normally ready signal. Note that if no device is selected the bus remainsready. Systems that have few or no devices requiring wait states usually implement a normallyready signal.The start of a bus cycle preloads a zero shifter and forces READY active (high). READY remainsactive if neither CS1 or CS2 goes low. Should either CS1 or CS2 go low, zeros are shifted out onevery rising edge of CLKOUT, causing READY to go inactive. At the end of the shift pattern,READY is forced active again. Assuming CS1 and CS2 are active just prior to phase 2 of T2,shifting one zero through the module causes two wait states. Each additional zero shifted throughthe module generates one wait state.3-16
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Page 44 and 45: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 78: Bus Interface Unit3
Page 81 and 82: BUS INTERFACE UNITPhysical Implemen
Page 83 and 84: BUS INTERFACE UNIT(X + 1)(X)A19:1 D
Page 85 and 86: BUS INTERFACE UNITFor word transfer
Page 87 and 88: BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
Page 89 and 90: BUS INTERFACE UNITCLKOUTT4or TI T1
Page 91 and 92: BUS INTERFACE UNITSignals From CPU4
Page 93: BUS INTERFACE UNITT2T3or TWT4or TIC
Page 97 and 98: BUS INTERFACE UNITT2or T3or TWT3or
Page 99 and 100: BUS INTERFACE UNITAn idle bus state
Page 101 and 102: BUS INTERFACE UNIT3.5.1.1 Refresh B
Page 103 and 104: BUS INTERFACE UNITMost memory and p
Page 105 and 106: BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
Page 107 and 108: BUS INTERFACE UNIT3.5.4 HALT Bus Cy
Page 109 and 110: BUS INTERFACE UNITCLKOUTT1 TI TIALE
Page 111 and 112: BUS INTERFACE UNITCLKOUTALES2:0AD15
Page 113 and 114: BUS INTERFACE UNITCLKOUTNMI/INTxNot
Page 115 and 116: BUS INTERFACE UNITALEProcessorA19:1
Page 117 and 118: BUS INTERFACE UNITThe WAIT instruct
Page 119 and 120: BUS INTERFACE UNITCLKOUTHOLD124HLDA
Page 121 and 122: BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
Page 123 and 124: BUS INTERFACE UNITCLKOUTHOLD12345HL
Page 126: Peripheral ControlBlock4
Page 129 and 130: PERIPHERAL CONTROL BLOCKRegister Na
Page 131 and 132: PERIPHERAL CONTROL BLOCK4.3 RESERVE
Page 133 and 134: PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
Page 135 and 136: PERIPHERAL CONTROL BLOCK4-8
Page 138 and 139: CHAPTER 5CLOCK GENERATION AND POWER
Page 140 and 141: CLOCK GENERATION AND POWER MANAGEME
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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