80C186EB/80C188EB Microprocessor User's Manual - CEUNES

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.3.2 Software InterruptsA Software Interrupt is caused by executing an “INTn” instruction. The n parameter correspondsto the specific interrupt type to be executed. The interrupt type can be any number between 0 and255. If the n parameter corresponds to an interrupt type associated with a hardware interrupt(NMI, Timers), the vectors are fetched and the routine is executed, but the corresponding bits inthe Interrupt Status register are not altered.The CPU processes software interrupts and exceptions in the same way. Software interrupts, exceptionsand traps cannot be masked.2.3.3 Interrupt LatencyInterrupt latency is the amount of time it takes for the CPU to recognize the existence of an interrupt.The CPU generally recognizes interrupts only between instructions or on instruction boundaries.Therefore, the current instruction must finish executing before an interrupt can berecognized.The worst-case 80C186 instruction execution time is an integer divide instruction with segmentoverride prefix. The instruction takes 69 clocks, assuming an 80C186 Modular Core family memberand a zero wait-state external bus. The execution time for an 80C188 Modular Core familymember may be longer, depending on the queue.This is one factor in determining interrupt latency. In addition, the following are also factors indetermining maximum latency:1. The CPU does not recognize the Maskable Interrupt unless the Interrupt Enable bit is set.2. The CPU does not recognize interrupts during HOLD.3. Once communication is completely established with an 80C187, the CPU does notrecognize interrupts until the numerics instruction is finished.The CPU can recognize interrupts only on valid instruction boundaries. A valid instructionboundary usually occurs when the current instruction finishes. The following is a list of exceptions:1. MOVs and POPs referencing a segment register delay the servicing of interrupts untilafter the following instruction. The delay allows a 32-bit load to the SS and SP without aninterrupt occurring between the two loads.2. The CPU allows interrupts between repeated string instructions. If multiple prefixesprecede a string instruction and the instruction is interrupted, only the one prefixpreceding the string primitive is restored.3. The CPU can be interrupted during a WAIT instruction. The CPU will return to the WAITinstruction.2-45