80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.3 INTERRUPTS AND EXCEPTION HANDLINGInterrupts and exceptions alter program execution in response to an external event or an errorcondition. An interrupt handles asynchronous external events, for example an NMI. Exceptionsresult directly from the execution of an instruction, usually an instruction fault. The user cancause a software interrupt by executing an “INTn” instruction. The CPU processes software interruptsin the same way that it handles exceptions.The 80C186 Modular Core responds to interrupts and exceptions in the same way for all deviceswithin the 80C186 Modular Core family. However, devices within the family may have differentInterrupt Control Units. The Interrupt Control Unit handles all external interrupt sources and presentsthem to the 80C186 Modular Core via one maskable interrupt request (see Figure 2-24).This discussion covers only those areas of interrupts and exceptions that are common to the80C186 Modular Core family. The Interrupt Control Unit is proliferation-dependent; see Chapter8, “Interrupt Control Unit,” for additional information.NMIMaskableInterruptRequestCPUInterruptAcknowledgeInterruptControlUnitExternalInterruptSourcesA1028-0AFigure 2-24. Interrupt Control Unit2.3.1 Interrupt/Exception ProcessingThe 80C186 Modular Core can service up to 256 different interrupts and exceptions. A 256-entryInterrupt Vector Table (Figure 2-25) contains the pointers to interrupt service routines. Each entryconsists of four bytes, which contain the Code Segment (CS) and Instruction Pointer (IP) ofthe first instruction in the interrupt service routine. Each interrupt or exception is given a typenumber, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that interrupttypes 0–31 are reserved for Intel and should not be used by an application program.2-39
OVERVIEW OF THE 80C186 FAMILY ARCHITECTUREMemoryAddress3FE3FC82807E7C52504E4C4A48464442403E3C3A3836343230TableEntryCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIP2 BytesVectorDefinitionType 255Type 32Type 31Type 22UserAvailableReservedType 21-Serial 0 TransType 20- Serial 0 RecType 19 - Timer 2Type 18 - Timer 1Type 17 - INT4Type 16 - Numerics(<strong>80C186EB</strong> only)Type 15 - INT3Type 14 - INT2MemoryAddress2E2C2A28262422201E1C1A18161412100E0C0A0806040200TableEntryCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIPCSIP2 BytesVectorDefinitionCS = Code Segment ValueIP = Instruction Pointer ValueType 13 - INT1Type 12 - INT0Type 9-11 - ReservedType 8 - Timer 0Type 7 - ESC OpcodeType 6 - UnusedOpcodeType 5 - ArrayBoundsType 4 - OverflowType 3 - BreakpointType 2 - NMIType 1 - Single-StepType 0 - Divide ErrorA1010-01Figure 2-25. Interrupt Vector TableWhen an interrupt is acknowledged, a common event sequence (Figure 2-26) allows the processorto execute the interrupt service routine.1. The processor saves a partial machine status by pushing the Processor Status Word ontothe stack.2-40
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
Page 15 and 16: CONTENTSTableTABLESPage1-1 Comparis
Page 17 and 18: CONTENTSEXAMPLESExamplePage5-1 Init
Page 20 and 21: CHAPTER 1INTRODUCTIONThe 8086 micro
Page 22 and 23: INTRODUCTIONEach chapter covers a s
Page 24 and 25: INTRODUCTION1.3.1 How to Use Intel'
Page 26: Overview of the80C186 FamilyArchite
Page 29 and 30: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 39: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 78: Bus Interface Unit3
Page 81 and 82: BUS INTERFACE UNITPhysical Implemen
Page 83 and 84: BUS INTERFACE UNIT(X + 1)(X)A19:1 D
Page 85 and 86: BUS INTERFACE UNITFor word transfer
Page 87 and 88: BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
Page 89 and 90: BUS INTERFACE UNITCLKOUTT4or TI T1
Page 91 and 92: BUS INTERFACE UNITSignals From CPU4
Page 93 and 94: BUS INTERFACE UNITT2T3or TWT4or TIC
Page 95 and 96: BUS INTERFACE UNITA normally not-re
Page 97 and 98: BUS INTERFACE UNITT2or T3or TWT3or
Page 99 and 100: BUS INTERFACE UNITAn idle bus state
Page 101 and 102: BUS INTERFACE UNIT3.5.1.1 Refresh B
Page 103 and 104: BUS INTERFACE UNITMost memory and p
Page 105 and 106: BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
Page 107 and 108: BUS INTERFACE UNIT3.5.4 HALT Bus Cy
Page 109 and 110: BUS INTERFACE UNITCLKOUTT1 TI TIALE
Page 111 and 112: BUS INTERFACE UNITCLKOUTALES2:0AD15
Page 113 and 114: BUS INTERFACE UNITCLKOUTNMI/INTxNot
Page 115 and 116: BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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