80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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INDEX80C187 Math Coprocessor, 12-2–12-8accessing, 12-10–12-11arithmetic instructions, 12-3–12-4bus cycles, 12-11clocking, 12-10code examples, 12-13–12-16comparison instructions, 12-5constant instructions, 12-6data transfer instructions, 12-3data types, 12-7–12-8design considerations, 12-10–12-11example floating point routine, 12-16exceptions, 12-13I/O port assignments, 12-10initialization example, 12-13–12-16instruction set, 12-2interface, 12-7–12-13and chip-selects, 6-14, 12-11and PCB location, 4-7exception trapping, 12-13generating READY, 12-11processor control instructions, 12-6testing for presence, 12-10transcendental instructions, 12-58259A Programmable Interrupt Controllers, 8-1and special fully nested mode, 8-8cascading, 8-7, 8-8interrupt type, 8-9priority structure, 8-882C59A Programmable Interrupt Controllerinterfacing with, 3-25–3-27AAddress and data bus, 3-1–3-616-bit, 3-1–3-5considerations, 3-78-bit, 3-5–3-6considerations, 3-7See also Bus cycles‚ Data transfersAddress bus, See Address and data busAddress space, See Memory space‚ I/O spaceAddressing modes, 2-27–2-36and string instructions, 2-34based, 2-30, 2-31, 2-32based index, 2-34, 2-35direct, 2-29immediate operands, 2-28indexed, 2-32, 2-33indirect, 2-36memory operands, 2-28register indirect, 2-30, 2-31register operands, 2-27AH register, 2-5AL register, 2-5, 2-18, 2-23ApBUILDER files, obtaining from BBS, 1-6Application BBS, 1-5ArchitectureCPU block diagram, 2-2device feature comparisons, 1-2family introduction, 1-1overview, 1-1, 2-1Arithmeticinstructions, 2-19–2-20interpretation of 8-bit numbers, 2-20Arithmetic Logic Unit (ALU), 2-1Array bounds trap (Type 5 exception), 2-44ASCII, defined, 2-37Asynchronous inputs, synchronizing, B-2Auxiliary Flag (AF), 2-7, 2-9AX register, 2-1, 2-5, 2-18, 2-23, 3-6BBase Pointer (BP)‚ See BP registerBaud Rate Compare Register (BxCMP), 10-12Baud Rate Counter Register (BxCNT), 10-11BBS, 1-5BCD, defined, 2-37Bit manipulation instructions, 2-21–2-22BOUND instruction, 2-44, A-8BP register, 2-1, 2-13, 2-30, 2-34Breakpoint interrupt (Type 3 exception), 2-44Bus cycles, 3-20–3-45address/status phase, 3-10–3-12and 80C187, 12-11and CSU, 6-14and Idle mode, 5-13and PCB accesses, 4-4and Powerdown mode, 5-16Index-1
INDEXand T-states, 3-9data phase, 3-13HALT cycle, 3-28–3-34and chip-selects, 6-4HALT state, exiting, 3-30–3-34idle states, 3-18instruction prefetch, 3-20interrupt acknowledge (INTA) cycles, 3-6,3-25–3-26, 8-9and chip-selects, 6-4operation, 3-7–3-20priorities, 3-44–3-45, 7-2read cycles, 3-20–3-21refresh cycles, 3-22, 7-4, 7-5control signals, 7-5, 7-6during HOLD, 3-41–3-43, 7-13–7-14wait states, 3-13–3-18write cycles, 3-22–3-25See also Data transfersBus hold protocol, 3-39–3-44and CLKOUT, 5-6and CSU, 6-15and Idle mode, 5-14and refresh cycles, 3-41–3-43, 7-13–7-14and reset, 5-9latency, 3-40–3-41Bus Interface Unit (BIU), 2-1, 2-3, 2-11, 3-1–3-45and DRAM refresh requests, 7-4and TCU, 9-1buffering the data bus, 3-35–3-37modifying interface, 3-34–3-37, 3-37relationship to RCU, 7-1synchronizing software and hardware events,3-37–3-38using a locked bus, 3-38–3-39using multiple bus masters, 3-39–3-44BX register, 2-1, 2-5, 2-30CCarry Flag (CF), 2-7, 2-9Chip-Select Unit (CSU), 6-1and HALT bus cycles, 3-28and READY, 6-11–6-12and wait states, 6-11–6-12block diagram, 6-3bus cycle decoding, 6-14examples, 6-15–6-20features and benefits, 6-1functional overview, 6-2–6-5programming, 6-5–6-15registers, 6-5–6-15system diagram, 6-16See also Chip selectsChip-selectsactivating, 6-4and 80C187 interface, 6-14, 12-11and bus hold protocol, 6-15and DRAM controllers, 7-1and guarded memory locations, 6-20and reserved I/O locations, 6-14enabling and disabling, 6-11initializing, 6-6–6-15methods for generating, 6-1multiplexed I/O port pins, 11-7overlapping, 6-12–6-14programming considerations, 6-14start address, 6-10, 6-14stop address, 6-10timing, 6-4CL register, 2-5, 2-21, 2-22CLKOUTand bus hold, 5-6and power management modes, 5-6and reset, 5-6Clock generator, 5-6–5-10and system reset, 5-6–5-7output, 5-6synchronizing CLKOUT and RESOUT, 5-6–5-7Clock sources, TCU, 9-12Code (programs)‚ See SoftwareCode segment, 2-5Counters‚ See Timer Counter Unit (TCU)CPU, block diagram, 2-2Crystal‚See OscillatorCS register, 2-1, 2-5, 2-6, 2-13, 2-23, 2-39, 2-41Customer service, 1-4CX register, 2-1, 2-5, 2-23, 2-25, 2-26DData, 3-6Data bus, See Address and data busData segment, 2-5Data sheets, obtaining from BBS, 1-6Index-2
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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Page 390 and 391: APPENDIX DINSTRUCTION SET OPCODESAN
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Page 412: Index
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