80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNITCLKOUTT4or TI T1 T2T3or TWT4or TIAddress/Status PhaseData PhaseA1113-0AFigure 3-9. T-State and Bus Phases3.4.1 Address/Status PhaseFigure 3-10 shows signal timing relationships for the address/status phase of a bus cycle. A buscycle begins with the transition of ALE and S2:0. These signals transition during phase 2 of theT-state just prior to T1. Either T4 or TI precedes T1, depending on the operation of the previousbus cycle (see Figure 3-8 on page 3-9).ALE provides a strobe to latch physical address information. Address is presented on the multiplexedaddress/data bus during T1 (see Figure 3-10). The falling edge of ALE occurs during themiddle of T1 and provides a strobe to latch the address. Figure 3-11 presents a typical circuit forlatching addresses.The status signals (S2:0) define the type of bus cycle (Table 3-1). S2:0 remain valid until phase1 of T3 (or the last TW, when wait states occur). The circuit shown in Figure 3-11 can also beused to extend S2:0 beyond the T3 (or TW) state.3-10