80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNITThe major factors that influence bus latency are listed below (in order from longest delay to shortestdelay).1. Bus Not Ready — As long as the bus remains not ready, a bus hold request cannot beserviced.2. Locked Bus Cycle — As long as LOCK remains asserted, a bus hold request cannot beserviced. Performing a locked move string operation can take several thousands of clocks.3. Completion of Current Bus Cycle — A bus hold request cannot be serviced until thecurrent bus cycle completes. A bus hold request will not separate bus cycles required tomove odd-aligned word data. Also, bus cycles with long wait states will delay theservicing of a bus hold request.4. Interrupt Acknowledge Bus Cycle — A bus hold request is not serviced until after anINTA bus cycle has completed. An INTA bus cycle drives LOCK active.5. Refresh Bus Cycles — A bus hold request is not serviced until after the refresh bus cyclehas completed. Refresh bus cycles have a higher priority than hold bus requests.3.7.1.2 Refresh Operation During a Bus HOLDUnder normal operating conditions, once HLDA has been asserted it remains asserted untilHOLD is removed. However, when a refresh bus request is generated, the HLDA output is removed(driven low) to signal the need for the BIU to regain control of the local bus. The BIU doesnot gain control of the bus until HOLD is removed. This procedure prevents the BIU from justarbitrarily regaining control of the bus.Figure 3-34 shows the timing associated with the occurrence of a refresh request while HLDA isactive. Note that HLDA can be as short as one clock in duration. This happens when a refreshrequest occurs just after HLDA is granted. A refresh request has higher priority than a bus holdrequest; therefore, when the two occur simultaneously, the refresh request occurs before HLDAbecomes active.3-41