80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNIT+5+5PRED Q Latched HLDAHLDACLRRESOUTHOLDA1310-0AFigure 3-35. Latching HLDAThe removal of HOLD must be detected for at least one clock cycle to allow the BIU to regainthe bus and execute a refresh bus cycle. Should HOLD go active before the refresh bus cycle iscomplete, the BIU will release the bus and generate HLDA.3.7.2 Exiting HOLDFigure 3-36 shows the timing associated with exiting the bus hold state. Normally a bus operation(e.g., an instruction prefetch) occurs just after HOLD is released. However, if no bus cycle ispending when leaving a bus hold state, the bus and associated control signals remain floating, ifthe system is in normal operating mode. (For signal states associated with Idle and Powerdownmodes, see “Temporarily Exiting the HALT Bus State” on page 3-30).3-43