80C186EB/80C188EB Microprocessor User's Manual - CEUNES

INTERRUPT CONTROL UNIT8.2.1 Typical Interrupt SequenceWhen the Interrupt Control Unit first detects an interrupt, it sets the corresponding bit in the InterruptRequest register to indicate that the interrupt is pending. The Interrupt Control Unit checksall pending interrupt sources. If the interrupt is unmasked and meets the priority criteria (see “PriorityResolution” on page 8-5), the Interrupt Control Unit asserts the maskable interrupt requestto the CPU, then waits for the interrupt acknowledge.When the Interrupt Control Unit receives the interrupt acknowledge, it passes the interrupt typeto the CPU. At that point, the CPU begin the interrupt processing sequence.(See “Interrupt/ExceptionProcessing” on page 2-39 for details.) The Interrupt Control Unit always passes the vectorthat has the highest priority at the time the acknowledge is received. If a higher priority interruptoccurs before the interrupt acknowledge, the higher priority interrupt has precedence.When it receives the interrupt acknowledge, the Interrupt Control Unit clears the correspondingbit in the Interrupt Request register and sets the corresponding bit in the In-Service register. TheIn-Service register keeps track of which interrupt handlers are being processed. At the end of aninterrupt handler, the programmer must issue an End-of-Interrupt (EOI) command to explicitlyclear the In-Service register bit. If the bit remains set, the Interrupt Control Unit cannot processany additional interrupts from that source.8.2.2 Priority ResolutionThe decision to assert the maskable interrupt request to the CPU is somewhat complicated. Thecomplexity is needed to support interrupt nesting. First, an interrupt occurs and the correspondingInterrupt Request register bit is set. The Interrupt Control Unit then asserts themaskable interrupt request to the CPU, if the pending interrupt satisfies these requirements:1. its Interrupt Mask bit is cleared (it is unmasked)2. its priority is higher than the value in the Priority Mask register3. its In-Service bit is cleared4. its priority is equal to or greater than that of any interrupt whose In-Service bit is setThe In-Service register keeps track of interrupt handler execution. The Interrupt Control Unituses this information to decide whether another interrupt source has sufficient priority to preemptan interrupt handler that is executing.8-5