80C186EB/80C188EB Microprocessor User's Manual - CEUNES

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.3.4 Interrupt Response TimeInterrupt response time is the time from the CPU recognizing an interrupt until the first instructionin the service routine is executed. Interrupt response time is less for interrupts or exceptionswhich supply their own vector type. The maskable interrupt has a longer response time becausethe vector type must be supplied by the Interrupt Control Unit (see Chapter 8, “Interrupt ControlUnit”).Figure 2-27 shows the events that dictate interrupt response time for the interrupts that supplytheir type. Note that an on-chip bus master, such as the DRAM Refresh Unit, can make use ofidle bus cycles. This can increase interrupt response time.First Instruction FetchFrom Interrupt RoutineIdleRead IPIdleRead CSIdlePush FlagsIdlePush CSPush IPIdleClocks5454443445Total 42A1030-0AFigure 2-27. Interrupt Response Factors2.3.5 Interrupt and Exception PriorityInterrupts can be recognized only on valid instruction boundaries. If an NMI and a maskable interruptare both recognized on the same instruction boundary, NMI has precedence. Themaskable interrupt will not be recognized until the Interrupt Enable bit is set and it is the highestpriority.2-46