80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSThe following listing gives the formal definition of theENTER instruction for all cases.LEVEL denotes the value of the second operand.Push BPSet a temporary value FRAME_PTR: = SPIf LEVEL > 0 thenRepeat (LEVEL - 1) times:BP:=BP - 2Push the word pointed to by BPEnd RepeatPush FRAME_PTREnd ifBP:=FRAME_PTRSP:=SP - first operandFigure A-1. Formal Definition of ENTERENTER treats a reentrant procedure as a procedure calling another procedure at the same lexicallevel. A reentrant procedure can address only its own variables and variables of higher-level callingprocedures. ENTER ensures this by copying only stack frame pointers from higher-level procedures.Block-structured high-level languages use lexical nesting levels to control access to variables ofpreviously nested procedures. For example, assume for Figure A-2 that Procedure A calls ProcedureB, which calls Procedure C, which calls Procedure D. Procedure C will have access to thevariables of Main and Procedure A, but not to those of Procedure B because Procedures C and Boperate at the same lexical nesting level.The following is a summary of the variable access for Figure A-2.1. Main has variables at fixed locations.2. Procedure A can access only the fixed variables of Main.3. Procedure B can access only the variables of Procedure A and Main.Procedure B cannot access the variables of Procedure C or Procedure D.4. Procedure C can access only the variables of Procedure A and Main.Procedure C cannot access the variables of Procedure B or Procedure D.5. Procedure D can access the variables of Procedure C, Procedure A and Main.Procedure D cannot access the variables of Procedure B.A-3
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONSMain Program (Lexical Level 1)Procedure A (Lexical Level 2)Procedure B (Lexical Level 3)Procedure C (Lexical Level 3)Procedure D (Lexical Level 4)A1001-0AFigure A-2. Variable Access in Nested ProceduresThe first ENTER, executed in the Main Program, allocates dynamic storage space for Main, butno pointers are copied. The only word in the display points to itself because no previous valueexists to return to after LEAVE is executed (see Figure A-3).BPSP15 0Old BPBPM*BPM = BP Value for MAINDisplay MainDynamicStorageMaina1002 0a pcFigure A-3. Stack Frame for Main at Level 1A1002-0AAfter Main calls Procedure A, ENTER creates a new display for Procedure A. The first wordpoints to the previous value of BP (BPM). The second word points to the current value of BP(BPA). BPM contains the base for dynamic storage in Main. All dynamic variables for Main willbe at a fixed offset from this value (see Figure A-4).A-4
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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Page 288 and 289: CHAPTER 11INPUT/OUTPUT PORTSMany ap
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Page 296 and 297: INPUT/OUTPUT PORTSRegister Name:Reg
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Page 300: Math Coprocessing12
Page 303 and 304: MATH COPROCESSING12.3 THE 80C187 MA
Page 305 and 306: MATH COPROCESSINGAvailable data typ
Page 307 and 308: MATH COPROCESSING12.3.1.5 Constant
Page 309 and 310: MATH COPROCESSINGIncreasing Signifi
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Page 315 and 316: MATH COPROCESSING80C186Modular Core
Page 317 and 318: MATH COPROCESSING$mod186$modc187nam
Page 320 and 321: CHAPTER 13ONCE MODEONCE (pronounced
Page 322: 80C186 InstructionSet Additions and
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Page 336 and 337: APPENDIX BINPUT SYNCHRONIZATIONMany
Page 338: Instruction SetDescriptionsC
Page 341 and 342: INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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