80C186EB/80C188EB Microprocessor User's Manual - CEUNES

REFRESH CONTROL UNITRegister Name:Register Mnemonic:Register Function:Refresh Base Address RegisterRFBASEDetermines upper 7 bits of refresh address.15 0RA19RA18RA17RA16RA15RA14RA13A1008-0ABitMnemonicBit NameResetStateFunctionRA19:13RefreshBase00HUppermost address bits for DRAM refreshcycles.NOTE:Reserved register bits are shown with gray shading. Reserved bits must be writtento a logic zero to ensure compatibility with future Intel products.Figure 7-6. Refresh Base Address Register7.7.2.2 Refresh Clock Interval RegisterThe Refresh Clock Interval Register (Figure 7-7) defines the time between refresh requests. Thehigher the value, the longer the time between requests. The down-counter decrements every fallingCLKOUT edge, regardless of core activity. When the counter reaches one, the Refresh ControlUnit generates a refresh request, and the counter reloads the value from the register.7-8