80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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SERIAL COMMUNICATIONS UNITReceptionCompleteReceiveShiftRegisterTo PCB8X BaudClockRXDPinQ Q Q Q Q Q Q QRB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7D D D D D D D DRXDSamplerSxRBUFShiftClockRS0 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8Channel Status LogicOE FERB8/PEDBRK1 DBRK0 RIRI RequestSignalSxSTSTo PCBA1283-0AFigure 10-2. RX Machine10-3
SERIAL COMMUNICATIONS UNITThe RX machine can detect several error conditions that may occur during reception:1. Parity errors — A parity error flag is set when the parity of the received data is incorrect.2. Framing errors — If a valid stop bit is not received when expected by the RX machine, aframing error flag is set.3. Overrun errors — If SxRBUF is not read before another reception completes, the old datain SxRBUF is overwritten and an overrun error flag is set. This indicates that data from anearlier reception has been lost.The RX machine also recognizes two different break characters. The shorter break character is Mbit times, where M is equal to the total number of bits (start + data + stop) in a frame. The longerbreak character is 2M + 3 bit times. A break character results in at least one null (all zero) characterwith a framing error being received. Other error flags could be set depending on the lengthof the break character and the mode of the serial port.10.1.1.2 TX MachineA block diagram of the TX machine is shown in Figure 10-3. The TX machine logic supports thefollowing features:• parity generation (even, odd or none)• Clear-to-Send• break character transmission• double-buffered operationA transmission begins by writing a byte to the Serial Transmit Buffer (SxTBUF) Register. SxT-BUF is a holding register for the transmit shift register. The contents of SxTBUF are transferredto the transmit shift register as soon as it is empty. If no transmission is in progress (i.e., the transmitshift register is empty), SxTBUF is copied immediately to the transmit shift register. If parityis enabled, the parity bits are calculated and appended to the transmit shift register during thetransfer. The start and stop bits are added when the data is transmitted. The Transmit Interrupt bit(TI) is set at the beginning of the stop bit time.Double buffering is a useful feature of the TX machine. When the transmit shift register is empty,the user can write two sequential bytes to SxTBUF. The first byte is transmitted immediately andthe second byte is held in SxTBUF until the first byte has been transmitted.10-4
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80C186EB/80C188EBMicroprocessorUser
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Information in this document is pro
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CONTENTS2.3.2 Software Interrupts .
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CONTENTS6.4.4 Enabling and Disablin
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CONTENTS10.2.2 Asynchronous Mode Pr
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CONTENTSFIGURESFigurePage2-1 Simpli
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CONTENTSFIGURESFigurePage6-9 Using
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CONTENTSTableTABLESPage1-1 Comparis
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CONTENTSEXAMPLESExamplePage5-1 Init
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CHAPTER 1INTRODUCTIONThe 8086 micro
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INTRODUCTIONEach chapter covers a s
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INTRODUCTION1.3.1 How to Use Intel'
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Overview of the80C186 FamilyArchite
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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Page 203 and 204: INTERRUPT CONTROL UNIT8.2.2.1 Prior
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Page 207 and 208: INTERRUPT CONTROL UNIT8.2.6 Edge an
Page 209 and 210: INTERRUPT CONTROL UNITTable 8-3. In
Page 211 and 212: INTERRUPT CONTROL UNIT.Register Nam
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Page 217 and 218: INTERRUPT CONTROL UNITReading the P
Page 219 and 220: INTERRUPT CONTROL UNITRegister Name
Page 221 and 222: INTERRUPT CONTROL UNIT3. Program th
Page 224 and 225: CHAPTER 9TIMER/COUNTER UNITThe Time
Page 226 and 227: TIMER/COUNTER UNITTimer 0 Timer 1 T
Page 228 and 229: TIMER/COUNTER UNITContinued From"A"
Page 230 and 231: TIMER/COUNTER UNITRegister Name:Reg
Page 236 and 237: TIMER/COUNTER UNITThe timer countin
Page 238 and 239: TIMER/COUNTER UNITTimer 0Serviced1I
Page 240 and 241: TIMER/COUNTER UNIT9.3.2 Synchroniza
Page 242 and 243: TIMER/COUNTER UNITlib_80186 segment
Page 244 and 245: TIMER/COUNTER UNIT$mod186nameexampl
Page 246 and 247: TIMER/COUNTER UNIT_CMPB equ word pt
Page 248: SerialCommunicationsUnit10
Page 251: SERIAL COMMUNICATIONS UNIT1 2 3 4 5
Page 255 and 256: SERIAL COMMUNICATIONS UNITThe Trans
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Page 259 and 260: SERIAL COMMUNICATIONS UNITRegister
Page 261 and 262: SERIAL COMMUNICATIONS UNITRegister
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Page 265 and 266: SERIAL COMMUNICATIONS UNITThe seria
Page 267 and 268: SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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Page 271 and 272: SERIAL COMMUNICATIONS UNITChannel_0
Page 273 and 274: SERIAL COMMUNICATIONS UNITmovmovmov
Page 275 and 276: SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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Page 279 and 280: SERIAL COMMUNICATIONS UNIT$mod186na
Page 281 and 282: SERIAL COMMUNICATIONS UNIT$mod186na
Page 283 and 284: SERIAL COMMUNICATIONS UNITcmp al, F
Page 285 and 286: SERIAL COMMUNICATIONS UNIT10-36
Page 288 and 289: CHAPTER 11INPUT/OUTPUT PORTSMany ap
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Page 294 and 295: INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
Page 296 and 297: INPUT/OUTPUT PORTSRegister Name:Reg
Page 298 and 299: INPUT/OUTPUT PORTSRegister Name:Reg
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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