80C186EB/80C188EB Microprocessor User's Manual - CEUNES

BUS INTERFACE UNITThe WAIT instruction suspends program execution until one of two events occurs: an interruptis generated, or the TEST input pin is sampled low. Unlike interrupts, the TEST input pin doesnot require that program execution be transferred to a new location (i.e., an interrupt routine isnot executed). In processing the WAIT instruction, program execution remains suspended as longas TEST remains high (at least until an interrupt occurs). When TEST is sampled low, programexecution resumes.The TEST input and WAIT instruction provide a mechanism to delay program execution until ahardware event occurs, without having to absorb the delay associated with servicing an interrupt.3.6.3 Using a Locked BusTo address the problems of controlling accesses to shared resources, the BIU provides a hardwareLOCK output. The execution of a LOCK prefix instruction activates the LOCK output.LOCK goes active in phase 1 of T1 of the first bus cycle following execution of the LOCK prefixinstruction. It remains active until phase 1 of T1 of the first bus cycle following the execution ofthe instruction following the LOCK prefix. To provide bus access control in multiprocessor systems,the LOCK signal should be incorporated into the system bus arbitration logic residing inthe CPU.During normal multiprocessor system operation, priority of the shared system bus is determinedby the arbitration circuits on a cycle by cycle basis. As each CPU requires a transfer over the systembus, it requests access to the bus via its resident bus arbitration logic. When the CPU gainspriority (determined by the system bus arbitration scheme and any associated logic), it takes controlof the bus, performs its bus cycle and either maintains bus control, voluntarily releases thebus or is forced off the bus by the loss of priority.The lock mechanism prevents the CPU from losing bus control (either voluntarily or by force)and guarantees that the CPU can execute multiple bus cycles without intervention and possiblecorruption of the data by another CPU. A classic use of the mechanism is the “TEST and SETsemaphore,” during which a CPU must read from a shared memory location and return data tothe location without allowing another CPU to reference the same location during the test and setoperations.Another application of LOCK for multiprocessor systems consists of a locked block move, whichallows high speed message transfer from one CPU’s message buffer to another. During the lockedinstruction (i.e., while LOCK is active), a bus hold or refresh request is recorded, but is not acknowledgeduntil completion of the locked instruction. However, LOCK has no effect on interrupts.As an example, a locked HALT instruction causes bus hold or refresh bus requests to beignored, but still allows the CPU to exit the HALT state on an interrupt.3-38