80C186EB/80C188EB Microprocessor User's Manual - CEUNES

CLOCK GENERATION AND POWER MANAGEMENT5.2.2.1 Entering Powerdown ModePowerdown mode is entered by executing the HLT instruction after setting the PWRDN bit in thePower Control Register (see Figure 5-9 on page 5-12). The HALT cycle turns off both the coreand peripheral clocks and disables the crystal oscillator. See Chapter 3, “Bus Interface Unit,” fordetailed information on HALT bus cycles. Figure 5-12 shows the internal and external waveformsduring entry into Powerdown mode.CLKINOSCOUTCLKOUTCPU CoreClockInternalPeripheralClockHalt CycleT4 or T1 T1 T2 TICLKIN togglesonly whenexternalfrequencyinput is usedIndeterminateS2:0ALE011A1121-0AFigure 5-12. Entering Powerdown ModeDuring the T2 phase of the HLT instruction, the core generates a signal called Enter_Powerdown.Enter_Powerdown immediately disables the internal CPU core and peripheral clocks. The processordisables the oscillator inverter during the next CLKOUT cycle. If the design uses a crystaloscillator, the oscillator stops immediately. When CLKIN originates from an external frequencyinput (EFI), Powerdown isolates the signal on the CLKIN pin from the internal circuitry. Therefore,the circuit may drive CLKIN during Powerdown mode, although it will not clock the device.5-17