80C186EB/80C188EB Microprocessor User's Manual - CEUNES

INPUT/OUTPUT PORTSRegister Name:Register Mnemonic:Register Function:Port Data Latch RegisterPxLTCH (P1LTCH, P2LTCH)Contains the data driven on pins programmed asoutput ports.15 0PL7PL6PL5PL4PL3PL2PL1PL0A1314-0ABitMnemonicBit NameResetStateFunctionPL7:0Port DataLatch 7:0FFHThe data written to a PL bit appears on pinsprogrammed as general-purpose output ports.NOTE:Reserved register bits are shown with gray shading. Reserved bits must be writtento a logic zero to ensure compatibility with future Intel products.Figure 11-7. Port Data Latch Register (PxLTCH)11.2.4 Port Pin State RegisterThe Port Pin State Register (Figure 11-8) is a read-only register that is used to determine the stateof a port pin. When the Port Pin State Register is read, the current state of the port pins is gatedto the internal data bus.11-10