80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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CONTENTSCHAPTER 1INTRODUCTION1.1 HOW TO USE THIS MANUAL....................................................................................... 1-21.2 RELATED DOCUMENTS .............................................................................................. 1-31.3 CUSTOMER SERVICE.................................................................................................. 1-41.3.1 How to Use Intel's FaxBack Service .........................................................................1-51.3.2 How to Use Intel's Application BBS ..........................................................................1-51.3.3 How to Find the Latest ApBUILDER Files, Hypertext <strong>Manual</strong>s, andData Sheets on the BBS ............................................................................................1-6CHAPTER 2OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE2.1 ARCHITECTURAL OVERVIEW .................................................................................... 2-12.1.1 Execution Unit ...........................................................................................................2-22.1.2 Bus Interface Unit .....................................................................................................2-32.1.3 General Registers .....................................................................................................2-42.1.4 Segment Registers ...................................................................................................2-52.1.5 Instruction Pointer .....................................................................................................2-62.1.6 Flags .........................................................................................................................2-72.1.7 Memory Segmentation ..............................................................................................2-82.1.8 Logical Addresses ...................................................................................................2-102.1.9 Dynamically Relocatable Code ...............................................................................2-132.1.10 Stack Implementation .............................................................................................2-152.1.11 Reserved Memory and I/O Space ...........................................................................2-152.2 SOFTWARE OVERVIEW ............................................................................................ 2-172.2.1 Instruction Set .........................................................................................................2-172.2.1.1 Data Transfer Instructions .............................................................................2-182.2.1.2 Arithmetic Instructions ...................................................................................2-192.2.1.3 Bit Manipulation Instructions .........................................................................2-212.2.1.4 String Instructions ..........................................................................................2-222.2.1.5 Program Transfer Instructions .......................................................................2-232.2.1.6 Processor Control Instructions ......................................................................2-272.2.2 Addressing Modes ..................................................................................................2-272.2.2.1 Register and Immediate Operand Addressing Modes ...................................2-272.2.2.2 Memory Addressing Modes ...........................................................................2-282.2.2.3 I/O Port Addressing .......................................................................................2-362.2.2.4 Data Types Used in the 80C186 Modular Core Family .................................2-372.3 INTERRUPTS AND EXCEPTION HANDLING ............................................................ 2-392.3.1 Interrupt/Exception Processing ...............................................................................2-392.3.1.1 Non-Maskable Interrupts ...............................................................................2-422.3.1.2 Maskable Interrupts .......................................................................................2-432.3.1.3 Exceptions .....................................................................................................2-43iii
CONTENTS2.3.2 Software Interrupts ..................................................................................................2-452.3.3 Interrupt Latency .....................................................................................................2-452.3.4 Interrupt Response Time ........................................................................................2-462.3.5 Interrupt and Exception Priority ...............................................................................2-46CHAPTER 3BUS INTERFACE UNIT3.1 MULTIPLEXED ADDRESS AND DATA BUS................................................................ 3-13.2 ADDRESS AND DATA BUS CONCEPTS..................................................................... 3-13.2.1 16-Bit Data Bus .........................................................................................................3-13.2.2 8-Bit Data Bus ...........................................................................................................3-53.3 MEMORY AND I/O INTERFACES................................................................................. 3-63.3.1 16-Bit Bus Memory and I/O Requirements ...............................................................3-73.3.2 8-Bit Bus Memory and I/O Requirements .................................................................3-73.4 BUS CYCLE OPERATION ............................................................................................ 3-73.4.1 Address/Status Phase ............................................................................................3-103.4.2 Data Phase .............................................................................................................3-133.4.3 Wait States ..............................................................................................................3-133.4.4 Idle States ...............................................................................................................3-183.5 BUS CYCLES .............................................................................................................. 3-203.5.1 Read Bus Cycles ....................................................................................................3-203.5.1.1 Refresh Bus Cycles .......................................................................................3-223.5.2 Write Bus Cycles .....................................................................................................3-223.5.3 Interrupt Acknowledge Bus Cycle ...........................................................................3-253.5.3.1 System Design Considerations .....................................................................3-273.5.4 HALT Bus Cycle ......................................................................................................3-283.5.5 Temporarily Exiting the HALT Bus State .................................................................3-303.5.6 Exiting HALT ...........................................................................................................3-323.6 SYSTEM DESIGN ALTERNATIVES ........................................................................... 3-343.6.1 Buffering the Data Bus ............................................................................................3-353.6.2 Synchronizing Software and Hardware Events .......................................................3-373.6.3 Using a Locked Bus ................................................................................................3-383.7 MULTI-MASTER BUS SYSTEM DESIGNS................................................................. 3-393.7.1 Entering Bus HOLD ................................................................................................3-393.7.1.1 HOLD Bus Latency ........................................................................................3-403.7.1.2 Refresh Operation During a Bus HOLD ........................................................3-413.7.2 Exiting HOLD ..........................................................................................................3-433.8 BUS CYCLE PRIORITIES ........................................................................................... 3-44iv
Page 1 and 2: 80C186EB/80C188EBMicroprocessorUser
Page 3: Information in this document is pro
Page 7 and 8: CONTENTS6.4.4 Enabling and Disablin
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Page 11 and 12: CONTENTSFIGURESFigurePage2-1 Simpli
Page 13 and 14: CONTENTSFIGURESFigurePage6-9 Using
Page 15 and 16: CONTENTSTableTABLESPage1-1 Comparis
Page 17 and 18: CONTENTSEXAMPLESExamplePage5-1 Init
Page 20 and 21: CHAPTER 1INTRODUCTIONThe 8086 micro
Page 22 and 23: INTRODUCTIONEach chapter covers a s
Page 24 and 25: INTRODUCTION1.3.1 How to Use Intel'
Page 26: Overview of the80C186 FamilyArchite
Page 29 and 30: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 39: OVERVIEW OF THE 80C186 FAMILY ARCHI
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit3
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BUS INTERFACE UNITPhysical Implemen
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BUS INTERFACE UNIT(X + 1)(X)A19:1 D
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BUS INTERFACE UNITFor word transfer
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BUS INTERFACE UNITCLKOUTT4 T1 T2 T3
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BUS INTERFACE UNITCLKOUTT4or TI T1
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BUS INTERFACE UNITSignals From CPU4
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BUS INTERFACE UNITT2T3or TWT4or TIC
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BUS INTERFACE UNITA normally not-re
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BUS INTERFACE UNITT2or T3or TWT3or
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BUS INTERFACE UNITAn idle bus state
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BUS INTERFACE UNIT3.5.1.1 Refresh B
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BUS INTERFACE UNITMost memory and p
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BUS INTERFACE UNITCLKOUTT4 T2 T3 TI
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BUS INTERFACE UNIT3.5.4 HALT Bus Cy
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BUS INTERFACE UNITCLKOUTT1 TI TIALE
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BUS INTERFACE UNITCLKOUTALES2:0AD15
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BUS INTERFACE UNITCLKOUTNMI/INTxNot
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BUS INTERFACE UNITALEProcessorA19:1
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BUS INTERFACE UNITThe WAIT instruct
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BUS INTERFACE UNITCLKOUTHOLD124HLDA
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BUS INTERFACE UNITCLKOUT1 3 4HOLDHL
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BUS INTERFACE UNITCLKOUTHOLD12345HL
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Peripheral ControlBlock4
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PERIPHERAL CONTROL BLOCKRegister Na
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PERIPHERAL CONTROL BLOCK4.3 RESERVE
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PERIPHERAL CONTROL BLOCK4.4.3.1 Wri
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PERIPHERAL CONTROL BLOCK4-8
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CHAPTER 5CLOCK GENERATION AND POWER
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit6
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CHIP-SELECT UNIT27C25674AC138A1:13A
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CHIP-SELECT UNITT4 T1 T2 T3T4CLKOUT
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CHIP-SELECT UNITThe START register
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CHIP-SELECT UNITRegister Name:Regis
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CHIP-SELECT UNIT6.4.2 Start Address
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CHIP-SELECT UNITBUS READYREADY Cont
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CHIP-SELECT UNITTable 6-3 lists exa
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CHIP-SELECT UNITREADYALEA19:16AD15:
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CHIP-SELECT UNITDRAM_BASEEQU 128 ;W
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CHIP-SELECT UNIT; DATA SEGMENTDATAS
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CHAPTER 7REFRESH CONTROL UNITThe Re
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REFRESH CONTROL UNITRefresh Control
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REFRESH CONTROL UNIT7.5 REFRESH BUS
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REFRESH CONTROL UNIT7.7 PROGRAMMING
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITRegister Name:R
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REFRESH CONTROL UNITmov dx, RFBASEm
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Interrupt ControlUnit8
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INTERRUPT CONTROL UNITTimer 0 Timer
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INTERRUPT CONTROL UNITInterrupt sou
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INTERRUPT CONTROL UNIT8.2.2.1 Prior
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INTERRUPT CONTROL UNITINTINT08259Ao
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INTERRUPT CONTROL UNIT8.2.6 Edge an
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INTERRUPT CONTROL UNITTable 8-3. In
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INTERRUPT CONTROL UNIT.Register Nam
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INTERRUPT CONTROL UNIT8.3.2 Interru
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INTERRUPT CONTROL UNIT8.3.4 Priorit
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INTERRUPT CONTROL UNITReading the P
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INTERRUPT CONTROL UNITRegister Name
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INTERRUPT CONTROL UNIT3. Program th
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CHAPTER 9TIMER/COUNTER UNITThe Time
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TIMER/COUNTER UNITTimer 0 Timer 1 T
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TIMER/COUNTER UNITContinued From"A"
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TIMER/COUNTER UNITRegister Name:Reg
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TIMER/COUNTER UNITThe timer countin
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TIMER/COUNTER UNITTimer 0Serviced1I
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TIMER/COUNTER UNIT9.3.2 Synchroniza
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TIMER/COUNTER UNITlib_80186 segment
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TIMER/COUNTER UNIT$mod186nameexampl
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TIMER/COUNTER UNIT_CMPB equ word pt
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SerialCommunicationsUnit10
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SERIAL COMMUNICATIONS UNIT1 2 3 4 5
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SERIAL COMMUNICATIONS UNITThe RX ma
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SERIAL COMMUNICATIONS UNITThe Trans
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SERIAL COMMUNICATIONS UNIT5. At the
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNITRegister
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SERIAL COMMUNICATIONS UNIT3. If the
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SERIAL COMMUNICATIONS UNITThe seria
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SERIAL COMMUNICATIONS UNIT10.2.3 Pr
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SERIAL COMMUNICATIONS UNITBCLK is a
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SERIAL COMMUNICATIONS UNITChannel_0
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SERIAL COMMUNICATIONS UNITmovmovmov
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SERIAL COMMUNICATIONS UNIT10.5.2 Mo
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SERIAL COMMUNICATIONS UNITMASTER186
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNIT$mod186na
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SERIAL COMMUNICATIONS UNITcmp al, F
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SERIAL COMMUNICATIONS UNIT10-36
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CHAPTER 11INPUT/OUTPUT PORTSMany ap
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INPUT/OUTPUT PORTS11.1.2 Input Port
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INPUT/OUTPUT PORTSFrom IntegratedPe
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INPUT/OUTPUT PORTS11.1.5.1 Port 1 O
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INPUT/OUTPUT PORTSRegister Name:Reg
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INPUT/OUTPUT PORTSRegister Name:Reg
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Math Coprocessing12
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MATH COPROCESSING12.3 THE 80C187 MA
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MATH COPROCESSINGAvailable data typ
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MATH COPROCESSING12.3.1.5 Constant
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MATH COPROCESSINGIncreasing Signifi
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MATH COPROCESSING12.4.1 Clocking th
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MATH COPROCESSINGExternalOscillator
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MATH COPROCESSING80C186Modular Core
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MATH COPROCESSING$mod186$modc187nam
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CHAPTER 13ONCE MODEONCE (pronounced
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80C186 InstructionSet Additions and
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX BINPUT SYNCHRONIZATIONMany
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Instruction SetDescriptionsC
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INSTRUCTION SET DESCRIPTIONSTable C
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INSTRUCTION SET DESCRIPTIONSINCINST
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INSTRUCTION SET DESCRIPTIONSOROUTTa
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INSTRUCTION SET DESCRIPTIONSC-48
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APPENDIX DINSTRUCTION SET OPCODESAN
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEXand T-states, 3-9data phase, 3
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INDEXarithmetic instructions, 2-19-
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INDEXblock diagram, 3-15implementat
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INDEXWWait statesand bus cycles, 3-
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80C186EB/80C188EB Microprocessor User's Manual - CEUNES

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