80C186EB/80C188EB Microprocessor User's Manual - CEUNES

TIMER/COUNTER UNITRegister Name:Register Mnemonic:Register Function:Timer 0 and 1 Control RegistersT0CON, T1CONDefines Timer 0 and 1 operation.15 0ENINHINTRIUMCRTGPEXTALTCONTA1297-0ABitMnemonicBit NameResetStateFunctionRTG Retrigger X This bit specifies the action caused by a low-to-hightransition on the TMR INx input. Set RTG to reset thecount; clear RTG to enable counting. This bit isignored with external clocking (EXT=1).P Prescaler X Set to increment the timer when Timer 2 reaches itsmaximum count. Clear to increment the timer at ¼CLKOUT. This bit is ignored with external clocking(EXT=1).EXTExternalClockXSet to use external clock; clear to use internal clock.The RTG and P bits are ignored with external clocking(EXT set).ALTAlternateCompareRegisterXThis bit controls whether the timer runs in single ordual maximum count mode (see Figure 9-4 on page9-6). Set to specify dual maximum count mode; clearto specify single maximum count mode.CONTContinuousModeXSet to cause the timer to run continuously. Clear todisable the counter (clear the EN bit) after eachcounting sequence.NOTE:Reserved register bits are shown with gray shading. Reserved bits must be written to alogic zero to ensure compatibility with future Intel products.Figure 9-5. Timer 0 and Timer 1 Control Registers (Continued)9-8